Noise Glitch Analysis: Step-by-Step Walkthrough

Step-by-step analysis walkthrough

Use when you own Noise Glitch Analysis in a timing war room.

1. Open signoff scenario list — note worst WNS corner.

2. report_timing -max/-min on failing group.

3. Trace launch and capture clocks on critical path.

4. Check exceptions and generated clocks on path.

5. Break down cell vs net delay.

6. Compare implementation vs signoff view if delta suspicious.

7. Assign owner: RTL, synth, PD, CTS, SI.

8. Propose ECO with hold/SI check plan.

9. Run regression matrix.

10. Update closure dashboard and memo.

Artifacts to collect

• noise report, victim waveform, fix list (spacing/shielding)

• SDC file

• SPEF tag

• MMMC scenario list

• ECO ticket

Decision memo template

STA DECISION MEMO — Noise Glitch Analysis
corner/mode:
WNS/TNS:
hypothesis:
ECO:
regression:
owners: SI owner, RTL owner, STA owner

Reference visuals

Glitch on quiet victim

VOLTAGE
  ^     glitch peak
  |    /\
  |___/  \_____ victim (should stay quiet)
      ^ may cause false toggle on input FF

STA deep dive

Coupling makes delay a function of neighbors, not just wire RC.

Concept diagram

SI ON VICTIM

victim net delay = base_RC + coupling_from_aggressors

Metric graph

DELTA DELAY ON CRITICAL PATHS

no SI   ████████  1.2ns
with SI ██████████  1.35ns  (+150ps)

Reports and artifacts

• delta delay report

• aggressor list

• noise peaks

• SI WNS delta

Mini case study

Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.

Debug branches

• Re-run SI after every timing ECO

• Shield wide switching buses

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Beyond delta delay, aggressors can inject glitches on quiet victims; noise analysis checks functional thresholds on sensitive inputs.

Metric: noise peak, glitch width, functional fail rate on SI-critical nets