Path Group War Room: Silicon PPA Impact

Silicon PPA and closure impact

Reproducible runs are as important as the fix.

Area drivers

• Upsize cells

• Buffer insertion

• Shield wires

Power drivers

• VT swap leakage

• Clock tree power for skew

Timing impact

• Net delay on critical routes

• SI delta delay

PD consequences

• Congestion limits sizing

• Layer promotion for nets

Verification burden

• ECO equivalence

• SI re-signoff

PPA — Path Group War Room
area/power/timing/closure-time tradeoff

PPA takeaways

• ECO has PPA cost

• Signoff is multi-corner

Design option PPA snapshot

BEFORE / AFTER ECO — Path Group War Room

WNS (ps)
  0 |                    --- target
-50 |    ● regressed
-80 |         ● before ECO
-20 |              ● after ECO
    +-------------------------------> ECO iteration
Prove setup AND hold moved safely.

STA deep dive

Debug hygiene separates senior STA leads from report readers.

Concept diagram

DEBUG ORDER

1. same tags?  2. constraints?  3. view?  4. real path?  5. ECO

Metric graph

ROOT CAUSE MIX (typical)

constraint bugs  ████████  35%
view mismatch    ██████    25%
real path        ██████    25%
methodology      ████      15%

Reports and artifacts

• run manifest

• SDC diff

• SPEF tag

• scenario isolation

Mini case study

Mystery regression: SPEF corner tag typo in run script — not a design bug.

Debug branches

• Manifest every run

• War room by path group

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

War rooms assign failing path groups to owning teams (RTL, synth, PD, CTS) based on delay breakdown and path class.

Metric: WNS per path group, endpoint owner assignment rate