Most ECO patches combine three edits. Spare cells add logic, rewiring moves connections, and resizing swaps a cell for an equivalent one.
All three keep the rest of the netlist untouched. The table below fixes each edit with one example.
Edit | What changes | Example |
|---|---|---|
Spare-cell use | An unused cell is wired into the cone | A spare NAND2 becomes the new AND term. |
Rewire | A net source or load changes, cell count unchanged | A load moves from the old net to the spare-cell output. |
Resize | A cell is swapped for an equivalent gate | A gate is exchanged to trade area against delay. |
The script below builds a two-output block with disjoint cones. In this disjoint toy the global per-type counts coincide with per-cone membership, and a general cone check selects by fanin from each output.
read_verilog <<EOV
module eco_cone(input wire a, b, c, output wire y1, y2);
wire n1 = a & b;
assign y1 = n1 | c;
assign y2 = a ^ b;
endmodule
EOV
hierarchy -check -top eco_cone
proc
flatten
opt
techmap
opt_clean
check
select -assert-count 1 t:$_AND_
select -assert-count 1 t:$_OR_
select -assert-count 1 t:$_XOR_
select -assert-count 2 t:$_AND_ t:$_OR_
select -assert-none t:$_MUX_
log PASS: y1 cone holds 2 cells and y2 cone holds 1 cell with no mux cellsIn this disjoint toy the y1 cone holds the AND and OR cells, 2 in total. The y2 cone holds the XOR cell, 1 in total, and no MUX cell appears anywhere.
Spare cells are placed before the change is known. The pool must cover the planned edits with margin.
EXAMPLE parameters (not tool defaults): 200 spare cells per block
first ECO edit consumes 3 cells: 200 - 3 = 197 remain
second ECO edit consumes 2 cells: 197 - 2 = 195 remain
used after both edits = 3 + 2 = 5 of 200 = 5 / 200 = 2.5%
rule used here: stop patching and re-run when the pool cannot cover the next editThe y1 cone, which holds the edited cell. In practice the whole block is re-proven, since a misidentified cone is itself a bug.
Patch. The pool covers 3 cells with 194 left, so the patch fits.