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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
    • Equivalence Checking
    • Incremental Compile and ECO
      • Re-run or Patch
      • Logic Cone Isolation
      • ECO Netlist Edits
      • Hierarchy and dont_touch
      • Equivalence and QoR Regression
    • Physical-Aware Synthesis and Handoff
  • Flows and Debugging15
  • Interview and Judgment11
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‹Incremental Compile and ECO
  1. Topics
  2. Logic Synthesis
  3. Verification, ECO and Handoff
  4. Incremental Compile and ECO
  5. Hierarchy and dont_touch

Part 7 · Verification, ECO and Handoff · Intermediate

Hierarchy and dont_touch

How hierarchy and dont_touch boundaries trade stability against QoR.

On this page

    What hierarchy preserves

    A hierarchy boundary stops optimisation from crossing between blocks. Each block keeps its own netlist while the change settles.

    Preserved blocks recompile faster and behave the same. The cost is missed optimisation across the boundary.

    Boundary

    Preserved

    Cost

    Kept hierarchy

    Block netlists and timing

    No cross-boundary optimisation.

    Flattened

    Nothing is preserved

    Every small change can move distant logic.

    What dont_touch preserves

    dont_touch excludes the marked logic from optimisation in that flow. It buys stability at the cost of frozen QoR, and the mark must be lifted on any cone being edited.

    Marks buy stability across runs. They also freeze suboptimal logic, so each mark trades quality against repeatability.

    A worked stability example

    Areas below are library units of the fictional teaching library course.lib, with NAND2 at 2 units and INV at 1 unit. The re-optimised outcome is a stated EXAMPLE value.

    Diagram
    block before the change: 40 NAND2 x 2 + 20 INV x 1 = 80 + 20 = 100 area units
    preserved boundary: 4 NAND2 become 4 NOR2 at 2 units each, 4 x 2 = 8 replaces 4 x 2 = 8, block stays 100 units, neighbours change by 0
    unpreserved re-optimisation (stated EXAMPLE outcome): block falls to 96 units, saving 100 - 96 = 4 of 100 = 4%
    churn comparison: 4 cells touched against 30 cells across 3 blocks

    Common mistakes

    Common pitfall

    Marking half the design dont_touch and expecting full-flow quality. Frozen logic cannot improve, so stability marks belong on settled blocks only.

    Interview

    Likely probes: stability against quality.

    • Hierarchy and dont_touch both trade optimisation room for repeatability.

    • The worked example buys zero neighbour churn for 4 area units kept.

    • Marks on moving logic freeze bugs in place instead of settling them.

    Check yourself A settled block carries dont_touch and a late change lands inside it. What must happen before the ECO?

    The mark must be lifted on the edited cone, else the tool keeps the old logic. The mark returns after the patch is proven.

    Check yourself Preserved hierarchy holds 100 units while flattening reaches 96. What do the 4 kept units buy?

    Stability and faster turnaround on single-block changes. Pay it on settled blocks, and optimise where the design still moves.

    Related topics

    • Re-run or Patch

    • Timing-Driven Synthesis

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    See also

    • Re-run or Patch
    • Logic Cone Isolation