The RAL Overview topic built the DMA's register model: five registers, one map, an adapter and a predictor. This topic is about using it, and about the dozen places where the model and the DUT quietly drift apart. Every lesson runs on the course bench's register layer, dma_ral_tb.sv, and every trap in it was hit for real while that bench was built: a trigger bit that update() refuses to write, a bit-bash that failed on 94 bits of a correct design, a backdoor peek that hid a real mismatch.
Say which of the three values (desired, mirrored, DUT) each access call moves, and pick the right call for a test, a sequence or a check.
Write a bus adapter that honours the full uvm_reg_adapter contract: provides_responses, byte enables, extensions and status.
Choose auto, explicit or passive prediction, and predict exactly where each one goes stale.
Model field behaviour with the built-in access policies, a custom policy name and a post_predict callback.
Use volatile fields, UVM_CHECK and check_on_read so mirror checks catch real bugs and nothing else.
Add backdoor access through HDL paths or a user backdoor class, and frontdoor access to indirect and serial registers.
# | Lesson | The question it answers |
|---|---|---|
1 | Which value does each call move, and why does | |
2 | What must an adapter promise, and what happens to the mirror on a bus error? | |
3 | Who updates the mirror, when, and what does each mode miss? | |
4 | How does the model know what a write does, and how do you teach it a rule it lacks? | |
5 | Which bits can a mirror check trust, and when does a check silently pass? | |
6 | How do you reach a register without the bus, and what does a peek do to the mirror? | |
7 | How do you access a register that has no address of its own? |