TLM FIFO Patterns Interview Q&A

[INT][SENIOR][UVM] MODEL ANSWER

Q: uvm_tlm_fifo vs direct analysis?

A:
  MECHANISM:  uvm_tlm_fifo provides put_export and get_export with internal queue —
              decouples producer rate from consumer rate. analysis_port has no buffer.
  MOTIVATION:  Producer faster than consumer, or clock domain crossing needs staging
              buffer between sample and process domains.
  WHEN:       analysis_fifo between monitor and slow scoreboard; tlm_fifo between
              generator put and driver get for pipeline staging.
  PITFALL:    Adding FIFO 'just in case' — adds latency and debug indirection when
              analysis direct connect suffices for same-rate same-domain TB.
  EXAMPLE:    1GHz monitor samples to 100MHz scb domain — analysis_fifo + get loop
              in scb clock domain processes buffered txn list.

[INT][SENIOR][UVM] MODEL ANSWER

Q: analysis_fifo vs tlm_fifo?

A:
  MECHANISM:  analysis_fifo accepts analysis write on input side, exposes get_export
              for blocking retrieval. tlm_fifo is pure put/get without analysis interface.
  MOTIVATION:  Bridge analysis producer (monitor) to get consumer (scoreboard task loop)
              without changing monitor to put_port.
  WHEN:       analysis_fifo: mon.ap.connect(fifo.analysis_export); scb get loop from
              fifo.get_export. tlm_fifo: explicit put/get both sides.
  PITFALL:    analysis_fifo unbounded — long sim memory growth if scb get loop stalls;
              monitor keeps writing, fifo grows forever.
  EXAMPLE:    mon.ap → analysis_fifo → scb.run_phase get loop compares one txn per
              iteration — decouples monitor sample from scb compare rate.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Bounded vs unbounded FIFO?

A:
  MECHANISM:  Unbounded FIFO grows until sim memory exhausted. Bounded FIFO rejects or
              blocks on put when full — exposes backpressure.
  MOTIVATION:  Unbounded hides producer overrun bugs; bounded forces explicit flow control
              policy matching DUT buffer limits.
  WHEN:       Bounded for DUT-model fidelity (FIFO depth = DUT buffer size). Unbounded
              only for short smoke sims or proven rate-matched paths.
  PITFALL:    Unbounded analysis_fifo in 12-hour stress sim — OOM kill on farm node,
              misdiagnosed as simulator bug.
  EXAMPLE:    DUT TX FIFO depth 16 — TB bounded fifo(16) with try_put backpressure
              when full; verifies DUT overflow handling under sustained load.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Scoreboard get loop from fifo?

A:
  MECHANISM:  scb run_phase: forever fifo.get_export.get(txn) — blocks until txn
              available, then compare logic. Separate from analysis write path.
  MOTIVATION:  Scoreboard compare may take multiple cycles — get loop processes at
              compare rate not sample rate.
  WHEN:       scb run_phase fork: get loop for actual, separate path for expected.
              analysis_fifo on actual path from monitor.
  PITFALL:    get loop without objection — scb run_phase exits immediately if empty
              task; must raise objection or fork loop with test umbrella objection.
  EXAMPLE:    scb run_phase raises objection, forks get_actual_loop and get_exp_loop,
              drops when both queues drained and test signals done.

[INT][SENIOR][UVM] MODEL ANSWER

Q: CDC with TLM FIFO?

A:
  MECHANISM:  Monitor samples in fast clock via analysis write to fifo; consumer get
              loop runs in slow clock domain process — FIFO holds txn objects safely
              if SV object references cross domain (not pin CDC — transaction CDC).
  MOTIVATION:  Transaction-level CDC decoupling — monitor never blocks on slow scb;
              fifo absorbs rate difference between clock domains.
  WHEN:       Multi-clock TB where monitor runs on bus clk, scoreboard on system clk.
  PITFALL:    Confusing transaction FIFO with pin-level CDC synchronizer — TLM fifo
              does not replace metastability flops on control signals.
  EXAMPLE:    AXI monitor @ 1GHz writes txn to fifo; scb @ 250MHz get loop processes —
              object handles safe; pin CDC still needs RTL synchronizers.

[INT][SENIOR][UVM] MODEL ANSWER

Q: FIFO between generator and driver?

A:
  MECHANISM:  Generator put_port → tlm_fifo → driver get_port — decouples sequence
              randomize rate from driver bus beat rate.
  MOTIVATION:  Pre-generate burst in fifo while driver still sending previous burst —
              maintains bus utilization on pipelined protocols.
  WHEN:       High-throughput stress when sequence body cannot keep up with driver
              consume rate; prefetch N items in fifo.
  PITFALL:    Deep fifo with uncoordinated item_done — driver consumes from fifo
              bypassing sequencer handshake, breaks sequence lifecycle tracking.
  EXAMPLE:    Prefetch fifo fed by background sequence, driver get from fifo instead
              of seq_item_port — non-standard, only for special perf harness not VIP.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Debug FIFO overflow/stall?

A:
  MECHANISM:  Monitor fifo.size() if API available; log put/get counts per component.
              Stall = get loop not running (objection leak) or fifo empty forever (no connect).
  MOTIVATION:  FIFO bugs manifest as scb empty compare or memory growth — count audit
              localizes producer vs consumer side.
  WHEN:       Log fifo depth at UVM_HIGH periodically; assert max depth bound in test.
              Compare monitor txn count vs fifo get count vs scb compare count.
  PITFALL:    Only checking scb mismatch — if get loop dead, fifo full, monitor blocked
              on analysis_fifo backpressure in some implementations.
  EXAMPLE:    monitor_txn=1000, fifo_get=0 — get loop never started (objection leak in
              scb run_phase fork); fix scb objection policy.

[INT][SENIOR][UVM] MODEL ANSWER

Q: FIFO type parameter rules?

A:
  MECHANISM:  uvm_tlm_fifo#(T) and uvm_tlm_analysis_fifo#(T) — T must match connected
              analysis_port and get consumer variable type exactly.
  MOTIVATION:  Same type safety as analysis path — fifo stores T objects in internal queue.
  WHEN:       Declare fifo #(axi_item) when monitor ap#(axi_item) and scb get axi_item.
  PITFALL:    fifo#(base_item) storing derived_item handles — SV polymorphism OK for
              handles but covergroup may need cast for derived fields.
  EXAMPLE:    fifo#(eth_frame) connected to mon ap#(eth_frame) — exact match;
              scb get eth_frame t processes without cast.