Part 11 · Senior Prep · Intermediate
Port, Export & Imp Interview Q&A
Model answers on uvm_port, uvm_export, uvm_imp roles, hierarchy connection rules, and parent-child TLM forwarding.
Port hierarchy fundamentals
The port/export/imp trio enforces hierarchical encapsulation — parent connects children without siblings knowing each other.
Q: port vs export vs imp — explain each role
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: port, export, imp?
A:
MECHANISM: port is initiator (calls methods outward). export is forwarder (passes
through to implementer below). imp is terminal implementer (executes method).
MOTIVATION: Hierarchy hides implementer — parent connects child port to sibling imp
without either child referencing the other's type directly.
WHEN: port on initiator (monitor ap, driver seq_item_port). imp on terminal
(scoreboard, driver). export on pass-through (agent analysis_export).
PITFALL: Connecting port-to-port — compile error; must be port→export or port→imp.
EXAMPLE: agt.mon.ap.connect(scb.act_imp) in env.connect_phase — port to imp.Q: Why cannot you connect port to port?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Why not port-to-port?
A:
MECHANISM: port initiates transaction; another port also initiates — no implementer
to execute the method. UVM connect rules require port→imp or port→export.
MOTIVATION: TLM enforces directed dataflow — every initiation path terminates at
an imp that implements the method body.
WHEN: Use export on intermediate hierarchy when parent must forward child
initiation to external implementer (agent export to env-level scb).
PITFALL: Attempting mon.ap.connect(other_mon.ap) — neither implements write().
EXAMPLE: Agent has mon.ap (port) and analysis_export (export forwarding to mon.ap);
env connects external subscriber to analysis_export.Q: Where do TLM connections happen in the phase timeline?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: TLM connections in which phase?
A:
MECHANISM: connect_phase bottom-up — all components and ports exist before connect
calls link port to imp/export.
MOTIVATION: build_phase creates port objects; connect_phase wires them after full
hierarchy elaboration — same rule as structural hierarchy.
WHEN: All port.connect() in connect_phase. env.connect links agents to scb/cov.
agent.connect links driver to sequencer internally.
PITFALL: connect in build_phase — sibling imp may not exist, silent no-connect or
null destination.
EXAMPLE: env.connect: agt[i].mon.ap.connect(scb.imp[i]) after all agents built.Q: How does parent forward child port through export?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Parent forward via export?
A:
MECHANISM: Child has imp or internal port. Parent declares export and connects
child port to export in parent connect_phase. External connects to export.
MOTIVATION: Agent encapsulates monitor — env should not reach into agt.mon.ap directly
if VIP policy hides internal structure (use agt.analysis_export).
WHEN: Reusable VIP agents expose analysis_export; env connects subscriber to export.
PITFALL: Export not connected to child port in agent.connect — external connect
succeeds but write() goes nowhere (analysis drop).
EXAMPLE: VIP agent: mon.ap.connect(analysis_export) in agent.connect. Env:
agt.analysis_export.connect(scb.imp) — env never touches mon.ap.Key takeaways
port initiates, imp implements, export forwards.
connect_phase only — port→imp or port→export, never port→port.
VIP agents expose export for external subscriber connection.
Common pitfalls
Port-to-port connection attempt — no implementer in chain.
Export not wired to child port — silent analysis drop.
Hierarchy and connection debug
Q: seq_item_port and seq_item_export — special case?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: seq_item_port special case?
A:
MECHANISM: uvm_seq_item_pull_port/export/imp implements pull model handshake —
get_next_item, item_done, put — not generic analysis write.
MOTIVATION: Driver-sequencer coupling is the canonical UVM pull pipeline — dedicated
port types enforce correct method set.
WHEN: driver.seq_item_port.connect(sequencer.seq_item_export) in agent.connect.
PITFALL: Connecting seq_item_port to generic uvm_port — type mismatch at compile.
EXAMPLE: agent.connect: drv.seq_item_port.connect(sqr.seq_item_export) — pull
pipeline for axi_item transactions.Q: How do you verify TLM connections are complete?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Verify TLM connections?
A:
MECHANISM: port.size() returns number of connected imps. end_of_elaboration check:
if (ap.size() == 0) uvm_warning — unconnected analysis port.
MOTIVATION: Unconnected analysis port silently drops transactions — size()==0 is
cheap audit before run_phase stimulus.
WHEN: end_of_elaboration in monitor (check ap.size()) and env (check scb imp).
UVM TLM GP display at UVM_HIGH for connect trace.
PITFALL: Only checking at scoreboard — monitor ap.size()==0 means no data ever
arrives, but scb check passes vacuously if imp connected but monitor not.
EXAMPLE: env end_of_elaboration: foreach agt[i] if (agt[i].mon.ap.size()==0)
uvm_error — catches forgotten connect in generate loop.diagram
[INT][SENIOR][UVM] TLM hierarchy (whiteboard)
env.connect_phase:
agt.mon.ap ──connect──► scb.imp
agt.mon.ap ──connect──► cov.analysis_export
agent.connect_phase:
drv.seq_item_port ──connect──► sqr.seq_item_export
mon.ap ──connect──► analysis_export (optional VIP pattern)Q: Multi-port scoreboard — how do imp declarations work?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Multi-port scoreboard imps?
A:
MECHANISM: uvm_analysis_imp_decl(_suffix) macro generates typed imp class per stream;
scoreboard implements write_tx and write_rx methods for dual-stream compare.
MOTIVATION: One scoreboard compares TX and RX streams — separate imps route to
different write methods without merge conflict.
WHEN: Dual-stream protocol (TX/RX), multi-channel compare, expected vs actual.
PITFALL: Single imp with write() for both streams — need tagged txn or merge logic
that obscures mismatch debug.
EXAMPLE: `uvm_analysis_imp_decl(_tx) and _rx; tx_imp and rx_imp connect to
respective monitor ports; write_tx and write_rx queue for compare.Q: Can imp be on a uvm_object (non-component)?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: imp on uvm_object?
A:
MECHANISM: uvm_analysis_imp #(T, OBJ, IMP) can attach to uvm_object subscriber —
subscriber is uvm_subscriber or custom object with write method.
MOTIVATION: Not every analysis consumer is a component — lightweight subscriber
objects can live inside scoreboard or coverage collector.
WHEN: uvm_subscriber#(txn) in coverage; custom imp on object for callback.
PITFALL: Object imp without parent component — connection from monitor still works
but phase lifecycle and hierarchy print omit the subscriber.
EXAMPLE: coverage_subscriber extends uvm_subscriber#(axi_item) — imp connects
to mon.ap; write() samples covergroup.Key takeaways
seq_item_pull_port is specialized pull pipeline — not generic port.
ap.size()==0 in end_of_elaboration catches silent unconnected analysis.
uvm_analysis_imp_decl enables multi-stream scoreboard write methods.
Common pitfalls
Checking scb connection but not monitor ap.size().
Single write() for dual-stream compare — debug opacity.