Part 11 · Senior Prep · Intermediate

Block-Level Baseline: Active Agents and Full Checking

Establishing the block testbench as the reusable foundation — active agents, complete scoreboard, coverage, and a stable config API for upstream integration.

Block TB as the reusable foundation

The block testbench is the source of truth for agent behavior, coverage, and checking. Subsystem and SoC TBs inherit — they do not reimplement.

diagram

[ARCH][SENIOR][UVM] block baseline stack

tb/top.sv
  interfaces + config_db vif push
    -> block_test
        -> block_env
            -> bus_agent [ACTIVE]
                mon -> coverage + analysis
                drv/sqr -> stimulus
            -> block_scoreboard
            -> reg_model (optional)
            -> virtual_sequencer

systemverilog

class block_env extends uvm_env;
  `uvm_component_utils(block_env)
  bus_agent agt;
  block_scoreboard sb;
  block_coverage cov;
  virtual block_sequencer v_sqr;

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    agt = bus_agent::type_id::create("agt", this);
    sb  = block_scoreboard::type_id::create("sb", this);
    cov = block_coverage::type_id::create("cov", this);
    v_sqr = block_sequencer::type_id::create("v_sqr", this);
  endfunction

  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    agt.mon.ap.connect(sb.act_export);
    agt.mon.ap.connect(cov.analysis_export);
    v_sqr.bus_sqr = agt.sqr;
  endfunction
endclass

Key takeaways

Block TB must be complete — do not defer checking to subsystem.
Publish agent analysis port as the integration boundary.
Virtual sequencer at block level enables scenario reuse upstream.

Common pitfalls

Block TB with no scoreboard — integration inherits the gap.
Hardcoded interface names in agent instead of cfg.if_name.
Coverage only at SoC level — block holes hide until too late.

Block config contract

Define a cfg object that captures every knob an integrator will need at higher levels.

Cfg object template

systemverilog

class bus_cfg extends uvm_object;
  `uvm_object_utils(bus_cfg)
  uvm_active_passive_enum is_active = UVM_ACTIVE;
  string if_name = "bus_if0";
  bit enable_coverage = 1;
  bit enable_scoreboard = 1;
  int unsigned max_outstanding = 8;

  function new(string name = "bus_cfg");
    super.new(name);
  endfunction
endclass

diagram

[ARCH][SENIOR][UVM] block cfg contract

integrator may set:
  is_active, if_name, enable_coverage, enable_scoreboard

integrator must NOT:
  poke driver internals
  override monitor packing
  bypass published analysis port

Block release checklist

Agent passes block-level smoke with directed + random sequences.
Scoreboard and coverage enabled by default in cfg.
README documents cfg fields and analysis port type.
Known limitations listed (what the VIP does NOT check).

bash

# block baseline smoke
simv +UVM_TESTNAME=block_smoke_test +UVM_VERBOSITY=UVM_LOW -l block_smoke.log
grep -E "UVM_ERROR|UVM_FATAL" block_smoke.log  # expect none

diagram

[ARCH] block sign-off criteria

smoke + random stress pass
and
coverage report reviewed against block plan
and
cfg API documented for integrators

Common pitfalls

Block VIP shipped without sequence library.
Scoreboard tied to internal item types not visible to integrator.
Block test that only runs directed — random stress deferred forever.

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