Part 11 · Senior Prep · Intermediate

Subsystem Integration: Composing Block VIPs

Integrating multiple block VIPs into a subsystem environment — integration scoreboards, cross-block scenarios, and config distribution without rewriting agents.

Subsystem composition model

Subsystem TB composes block VIPs and adds integration checking — address routing, DMA paths, interrupt fan-in — without modifying block agent internals.

diagram

[ARCH][SENIOR][UVM] subsystem composition

subsystem_env
  ├─ cpu_block_env    (reuse block VIP)
  ├─ dma_block_env    (reuse block VIP)
  ├─ mem_block_env    (reuse block VIP)
  ├─ integration_sb   (cross-block checks)
  └─ subsystem_v_sqr  (multi-block scenarios)

principle: block agents unchanged, integration layer added

systemverilog

class subsystem_env extends uvm_env;
  cpu_block_env cpu_env;
  dma_block_env dma_env;
  integration_scoreboard integ_sb;
  subsystem_virtual_sequencer sub_v_sqr;

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    cpu_env = cpu_block_env::type_id::create("cpu_env", this);
    dma_env = dma_block_env::type_id::create("dma_env", this);
    integ_sb = integration_scoreboard::type_id::create("integ_sb", this);
    sub_v_sqr = subsystem_virtual_sequencer::type_id::create("sub_v_sqr", this);
  endfunction

  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    cpu_env.agt.mon.ap.connect(integ_sb.cpu_export);
    dma_env.agt.mon.ap.connect(integ_sb.dma_export);
    sub_v_sqr.cpu_sqr = cpu_env.v_sqr;
    sub_v_sqr.dma_sqr = dma_env.v_sqr;
  endfunction
endclass

Key takeaways

Subsystem adds integration layer — do not fork block agents.
Integration scoreboard owns cross-block protocol checks.
Virtual sequencer coordinates multi-block scenarios.

Common pitfalls

Modifying block agent source for subsystem-specific hacks.
No integration scoreboard — cross-block bugs found only at SoC.
Subsystem cfg that duplicates block cfg fields inconsistently.

Integration checking patterns

Integration scoreboards observe multiple analysis streams and check cross-block invariants.

Cross-block check examples

diagram

[ARCH][SENIOR][UVM] integration check catalog

address map:
  CPU txn to addr X routes to MEM block monitor

DMA path:
  DMA write on port A appears as MEM write on port B

interrupt:
  block A event triggers block B status within N cycles

ordering:
  posted writes visible before subsequent reads

systemverilog

class integration_scoreboard extends uvm_scoreboard;
  uvm_analysis_export #(cpu_item) cpu_export;
  uvm_analysis_export #(dma_item) dma_export;
  cpu_item cpu_q[$];
  dma_item dma_q[$];

  function new(string name, uvm_component parent);
    super.new(name, parent);
    cpu_export = new("cpu_export", this);
    dma_export = new("dma_export", this);
  endfunction

  function void write_cpu(cpu_item t);
    cpu_q.push_back(t);
    check_routing(t);
  endfunction

  function void check_routing(cpu_item t);
    if (t.addr inside {[MEM_BASE:MEM_BASE+MEM_SIZE]})
      `uvm_info("INTEG", "CPU txn routed to MEM region", UVM_HIGH)
  endfunction
endclass

Subsystem scenario patterns

Virtual sequences on subsystem_v_sqr fork block-level sub-sequences.
Scenario cfg selects which blocks participate and their ordering.
Integration tests focus on handshakes between blocks, not re-proving block protocol.
Reuse block sequence library inside subsystem virtual sequences.

systemverilog

class dma_to_mem_seq extends uvm_sequence;
  task body();
    fork
      dma_block_seq.start(p_sequencer.dma_sqr);
      mem_block_seq.start(p_sequencer.mem_sqr);
    join
  endtask
endclass

diagram

[ARCH] subsystem review gate

block VIPs unmodified from block release
and
integration_sb covers cross-block plan items
and
subsystem vseq library maps to verification plan sections

Common pitfalls

Subsystem test that re-proves every block protocol corner.
Integration SB comparing unrelated transaction types without conversion.
Virtual sequencer exposing block env internals instead of v_sqr handles.

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