Part 11 · Senior Prep · Intermediate

SoC Multi-Domain: Power, Clock, and Chip Composition

Composing subsystem environments into chip-level verification — multi-clock domains, power islands, passive monitoring, and software-like stimulus patterns.

SoC composition architecture

Chip-level TB is mostly passive observation plus chip scoreboard and software-like scenarios — RTL drives most interfaces; VIPs monitor and check.

diagram

[ARCH][SENIOR][UVM] SoC TB architecture

chip_env
  ├─ cpu_subsystem_env   (passive on internal buses)
  ├─ io_subsystem_env    (mix: active on chip pins, passive inside)
  ├─ chip_scoreboard     (end-to-end SW-visible checks)
  ├─ power_domain_mgr    (reset/clock coordination)
  └─ chip_virtual_sqr    (SW-like boot + traffic scenarios)

stimulus: firmware images, register sequences, high-level vseqs

systemverilog

class chip_env extends uvm_env;
  cpu_subsystem_env cpu_subsys;
  io_subsystem_env io_subsys;
  chip_scoreboard chip_sb;

  function void build_phase(uvm_phase phase);
    chip_cfg cfg;
    super.build_phase(phase);
    if (!uvm_config_db#(chip_cfg)::get(this, "", "cfg", cfg))
      `uvm_fatal("CHIP", "chip_cfg missing")
    cpu_subsys = cpu_subsystem_env::type_id::create("cpu_subsys", this);
    io_subsys  = io_subsystem_env::type_id::create("io_subsys", this);
    chip_sb    = chip_scoreboard::type_id::create("chip_sb", this);
    apply_passive_defaults(cfg);
  endfunction

  function void apply_passive_defaults(chip_cfg cfg);
    cfg.cpu_is_active = UVM_PASSIVE;
    cfg.io_pin_active = UVM_ACTIVE;  // drive chip-level pins only
  endfunction
endclass

Key takeaways

SoC TB observes RTL-driven traffic — passive agents dominate.
Chip scoreboard checks end-to-end SW-visible behavior.
Power/clock domain coordination is a first-class architecture concern.

Common pitfalls

Active block agents inside chip TB driving already-driven buses.
No chip-level scoreboard — only block checks that miss integration.
Ignoring clock domain crossing in monitor/scoreboard sampling.

Multi-domain coordination

Power islands, clock gating, and reset sequencing require explicit TB architecture — not ad hoc delays.

Domain management patterns

diagram

[ARCH][SENIOR][UVM] multi-domain concerns

clock domains:
  monitors sample in correct clocking block
  scoreboard tags txn with domain ID

power islands:
  agents disable checking during power-down
  reset_phase re-syncs monitors after power-up

CDC:
  gray-code / handshake checks at domain boundaries

systemverilog

class power_domain_mgr extends uvm_component;
  function void reset_domain(string domain_id);
    `uvm_info("PWR", $sformatf("resetting domain %s", domain_id), UVM_LOW)
    // coordinate agent cfg, scoreboard flush, coverage sample boundary
  endfunction

  task wait_domain_ready(string domain_id);
    wait (power_state[domain_id] == PWR_ON);
    @(posedge clk[domain_id]);
  endtask
endclass

Software-like stimulus at chip level

Boot sequences load memory via backdoor or frontdoor RAL.
Chip virtual sequences mimic driver/firmware init order.
Stimulus through pin-level agents only where RTL expects external masters.
Long scenarios use objection policy suited for firmware runtime.

systemverilog

class chip_boot_vseq extends uvm_sequence;
  task body();
    // 1) release chip reset via RAL
    // 2) load firmware image to SRAM
    // 3) deassert CPU halt
    // 4) wait for boot marker in chip scoreboard
    chip_sb.wait_boot_complete(10ms);
  endtask
endclass

bash

# chip-level regression slice
simv +UVM_TESTNAME=chip_boot_test \
     +firmware=tests/images/bl1.hex \
     +UVM_TIMEOUT=50000000 \
     -l chip_boot.log

Common pitfalls

Chip test with block-level timeout values — instant false timeout.
Monitors sampling on wrong clock after dynamic frequency change.
Power-down during active scoreboard compare — stale queue corruption.

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