CPI and IPC

Instructions per cycle is IPC = instructions / cycles. Cycles per instruction is CPI = cycles / instructions, which equals 1 / IPC.

Elapsed time follows from cycles and frequency: time = cycles / frequency. Assume a 3 GHz core retires 2.4e9 instructions in 3.0e9 cycles.

IPC  = 2.4e9 inst / 3.0e9 cycles = 0.80
CPI  = 3.0e9 cycles / 2.4e9 inst = 1.25
time = 3.0e9 cycles / 3.0e9 cycles/s = 1.00 s

CPI decomposes into a base plus one penalty term per miss class: CPI = CPI_base + sum(rate_i x penalty_i). Assume CPI_base 1.0, a 5 percent data-miss rate with 10-cycle penalty, and a 2 percent mispredict rate with 15-cycle penalty.

CPI = 1.0 + 0.05 x 10 + 0.02 x 15
    = 1.0 + 0.50 + 0.30
    = 1.80

Miss and branch rates

Misses per kilo-instructions is MPKI = misses x 1000 / instructions. It stays comparable across runs of different length because instructions are the denominator.

Assume 200,000 last-level misses and 150,000 branch mispredicts over 50 million instructions.

LLC MPKI    = 200000 x 1000 / 50000000 = 4.0
branch MPKI = 150000 x 1000 / 50000000 = 3.0

Latency and bandwidth

Average memory access time is AMAT = hit_latency + miss_rate x miss_penalty. Assume a 2-cycle hit, a 4 percent miss rate, and a 120-cycle miss penalty.

Sustained bandwidth is accesses/s x bytes/access, capped by the slowest of link, controller, and DRAM. Assume 312.5 million 64-byte accesses per second.

AMAT = 2 + 0.04 x 120 = 2 + 4.8 = 6.8 cycles
BW   = 312.5e6 x 64 B = 20.0e9 B/s = 20 GB/s

Related topics

• Memory bandwidth and latency

Common mistakes

Equal IPC can hide different stress patterns, so IPC alone never declares success. Always pair it with the stall composition from the top-down lesson.