Hazards and Forwarding Networks — Extended Case Study

Extended case study

A review is called because a workload regresses after a Hazards and Forwarding Networks change.

Background

A stable baseline existed until a Pipeline Fundamentals change improved one benchmark and regressed a product workload on Hazard stall + forwarding correctness dashboard.

Symptoms observed

• Regression in Hazard stall + forwarding correctness dashboard

• Sim vs silicon disagreement

• Pressure to revert or ship risk

Investigation timeline

1. Freeze tags

2. Reproduce

3. Cluster

4. Experiment

5. Validate

6. Memo

Root cause

A hidden assumption in Hazards and Forwarding Networks failed under an unrepresented workload phase.

Fix and validation

• Replay failing trace with architectural checker and operand provenance logging.

• Validate scoreboard state transitions for allocate, forward, retire, and kill.

• Probe forwarding mux select and ready signals at cycle granularity around mismatch.

• Stress with synthetic dependency chains to isolate one hazard class at a time.

• Run formal/property checks for mutually exclusive source select and stale-data prevention.

Lessons learned

• Workload coverage beats clever microarchitecture

• Every change needs rollback triggers

HAZARD HEALTH SNAPSHOT
workload: vector_crypto_mix
ipc: 1.41
raw_stall_cycles_pct: 22.6
structural_stall_cycles_pct: 6.8
forward_success_rate_pct: 93.2
operand_mismatch_events: 17
top_signature: lane3_FMA_dep_chain
action: enforce age-priority select and add replay fence for exception window

Architecture deep dive

Pipeline depth and width are bets on branch predictability and cache behavior.

Concept diagram

PIPELINE VIEW

Fetch ──► Decode ──► Rename ──► Issue ──► Execute ──► Memory ──► Commit
  │         │          │          │          │          │          │
  ▼         ▼          ▼          ▼          ▼          ▼          ▼
I-cache   decode     ROB/RS     wakeup     ALU/BR     LSU       retire
miss      bubbles    full       select     latency    miss      bandwidth

Every pipeline discussion should name where bubbles enter and where they retire.

Metric graph

STALL STACK EXAMPLE

cycles (%)
frontend       ██████████████  28
branch         ████████        16
backend        ████████████    24
memory         █████████       18
retire/other   ██████          12

Read this before saying "make the pipe wider."

Metrics and artifacts

• IPC/CPI breakdown

• stall cycles by stage

• branch mispredict rate

• frontend vs backend bound

Mini case study

IPC drops after widening decode but branch-heavy workload shows frontend stalls unchanged. The correct read: backend was not the bottleneck — branch prediction and fetch bandwidth need investment first.

Debug branches

• If IPC flat after deeper pipeline, check branch MPKI and cache miss stalls.

• If hold timing fails on critical path, architecture may need shorter pipeline stage — link PD.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.