A crossing is a physical path with delay, so timing analysis has an opinion about it. Across related clocks it checks setup and hold exactly as it does inside one domain. Across asynchronous clocks there is nothing stable to check against, so the methodology replaces the ordinary check with two weaker but meaningful ones: the synchroniser structure is verified, and the short paths around it are bounded.
Clock relationship | What STA checks | What it cannot check |
|---|---|---|
Same clock | Setup and hold on every path | Nothing special; the ordinary contract holds |
Related clocks | Setup and hold against the known phase relationship | Crossings where the relationship is not actually guaranteed |
Asynchronous clocks | Nothing by default once the pair is declared asynchronous | Whether the crossing is functionally safe; that is the CDC analysis job |
Declaring a pair asynchronous therefore transfers responsibility: timing stops watching, and the CDC structural check becomes the only guard. That transfer is safe only when the structural check actually covers every path the declaration released.
The first synchroniser flop still has a timing requirement, even though the path into it is asynchronous. Its input must arrive with enough margin that the flop samples a settled value in the normal case, leaving the full clock period for the rare case when it does not.
The path from the source register to the first synchroniser flop must be bounded: short, with no logic on it, so the data is stable long before the sampling edge.
There must be no logic between the synchroniser flops: any gate there eats directly into the settling time the second flop relies on.
Only the last flop fans out to destination logic, so at most one controlled point can ever carry an unresolved value.
These are the same hygiene rules taught with the circuit in synchronisers. Timing analysis enforces the bounded part; CDC analysis enforces the structural part; neither enforces both, which is why signoff needs both.
It does not check that a synchroniser exists: a declared-asynchronous path with no synchroniser passes timing silently.
It does not check protocols: handshakes, Gray ordering, and FIFO full/empty logic are invisible to it.
It does not check reconvergence: two timed paths can still disagree by a cycle at their meeting point.
No. The declaration removed the path from timing checks, so timing passing is automatic. Correctness of the synchroniser is established by structural CDC analysis, not by STA.
Because any gate delay between them subtracts from the settling time available before the second flop samples. The whole point of the second flop is a full period of settling, and logic in between spends it.