CDC / RDC · All levels

Synchronizer Selection Guide: Theory Deep Dive

Theory Deep Dive for Synchronizer Selection Guide.

Foundational theory

Synchronizer Selection Guide anchors Metastability & Synchronizers. Crossing intent (level, pulse, bus, control/data coupling) determines legal synchronization topology and verification evidence. Senior signoff discussions tie every warning to mechanism class, operational mode, and risk containment evidence.

Core concepts explained

  • Crossing intent (level, pulse, bus, control/data coupling) determines legal synchronization topology and verification evidence.

  • Primary metric: crossing class coverage, incorrect pattern usage rate, waiver count

  • Primary artifact: crossing taxonomy matrix, approved synchronizer templates, waiver policy

  • Owners: CDC lead, methodology owner, design lead

  • Distinguish structural cleanliness from functional correctness.

  • Tie every waiver to silicon-risk framing and expiry.

Why this matters at signoff

At tapeout, unresolved CDC/RDC issues become latent reliability bugs. Metastability is probabilistic physics managed through architecture and timing assumptions.

Mental model

diagram
Crossing type -> Recommended structure

single-bit level   -> 2FF / 3FF sync
single-bit pulse   -> toggle/ack pulse sync
multi-bit payload  -> async FIFO or handshake bundle
status flags       -> gray pointer or token

Worked intuition

  1. Classify crossing intent and direction.

  2. Name clock/reset relationship assumptions.

  3. Inspect primary metric: crossing class coverage, incorrect pattern usage rate, waiver count.

  4. Collect structural plus dynamic evidence.

  5. Differentiate real hazard from tool noise.

  6. Pick smallest safe fix and define regression matrix.

  7. Document signoff rationale or waiver ownership.

Common misconceptions

  • CDC clean report means protocol is proven.

  • All resets are equivalent if assertion works.

  • Gray code alone guarantees FIFO correctness.

  • Waivers are harmless schedule shortcuts.

Visual reinforcement

Pattern selection map

diagram
Crossing type -> Recommended structure

single-bit level   -> 2FF / 3FF sync
single-bit pulse   -> toggle/ack pulse sync
multi-bit payload  -> async FIFO or handshake bundle
status flags       -> gray pointer or token

Layer responsibilities

diagram
CDC/RDC OWNERSHIP LAYERS — Synchronizer Selection Guide

layer                 owns                            common failure
------------------    -----------------------------   -----------------------------
design intent         crossing architecture           wrong topology selected
protocol semantics    req/ack, fifo, ordering        liveness/deadlock bugs
reset behavior        assert/deassert sequencing      boot instability
analysis setup        tool rules + waivers            false confidence
signoff governance    risk acceptance + dashboard     stale critical waivers

CDC/RDC deep dive

Metastability is managed risk, not eliminated risk.

Concept diagram

diagram
METASTABILITY FLOW

async event -> first sample may metastabilize
 -> settle window
 -> downstream sample confidence

Metric graph

diagram
MTBF TREND

target MTBF ---------
current design   ____/

Reports and artifacts

  • MTBF assumptions

  • synchronizer inventory

  • crossing class summary

  • critical waivers

Mini case study

Pulse sync chosen for a level signal caused intermittent stuck state under voltage stress.

Debug branches

  • Validate crossing class first

  • Check pulse width assumptions

  • Audit synchronizer template usage

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

  • State crossing class, assumptions, and owner with every issue.

  • Run structural and dynamic regressions after each fix.

Common pitfalls

  • Treating all warnings as equivalent risk.

  • Waiving issues without containment evidence.

  • Skipping reset and reconvergence stress after CDC fixes.

Theory reinforcement

Metastability is probabilistic physics managed through architecture and timing assumptions.