VLSI DV Interview Puzzles · All levels
SVA Assertion Puzzles: Tricky Q&A
Rapid-fire interview Q&A for SVA Assertion Puzzles.
Section Q&A
Rapid-fire questions an interviewer asks around SVA Assertion Puzzles. Answer out loud, then check yourself.
Q1. When should you prefer sequence and over intersect in interview problems?
Answer: Use and when both branches must match from the same start but can end at different cycles. Use intersect only when both start and end cycles must align exactly.
Trap: Treating and and intersect as interchangeable logical conjunctions.
Q2. An implication assertion is green, but req activity never happened. What is the technically correct verdict and practical risk?
Answer: The verdict is VACUOUS-PASS. Practical risk is false confidence: you proved implication logic under zero triggering, not protocol behavior under traffic.
Trap: Reporting vacuous pass as equivalent to fully exercised protocol proof.
Q3. Why does disable iff often hide expected failures during reset pulses?
Answer: disable iff aborts active assertion threads when its condition becomes true, so in-flight obligations are discarded rather than failed.
Trap: Assuming reset masking means 'pause and resume later' instead of 'terminate current attempts'.
Q4. What is the most common off-by-one mistake with |=> and ## ranges?
Answer: People forget |=> already advances checking by one cycle, then they mentally add another extra shift when evaluating ##[m:n] windows.
Trap: Evaluating non-overlapped implication consequents on the antecedent cycle.