VLSI DV Interview Puzzles · All levels

Intersect Requirement in Dual Checks

Property intent: one cycle after a rises, both b and c checks should align in the same endpoint cycle via intersect. Timeline: C90 a rises, C91 b=1 c=0, C92 c=1. Determine the verdict.

Puzzle

Difficulty: Medium · Puzzle 6 of 6 · Topic: Assertion Debug Puzzles

Property intent: one cycle after a rises, both b and c checks should align in the same endpoint cycle via intersect. Timeline: C90 a rises, C91 b=1 c=0, C92 c=1. Determine the verdict.

Code

systemverilog

property p_dual_same_cycle;
  @(posedge clk) $rose(a) |-> ((##1 b) intersect (##1 c));
endproperty

Hint

Both intersect branches must end in the same cycle (here, both at C91).

Step-by-step solution

diagram

1) $rose(a) at C90 triggers consequent.
2) ##1 b checks b at C91 and succeeds.
3) ##1 c checks c at C91 and fails because c=0 there.
4) intersect therefore fails immediately.

Answer

Answer: FAIL - intersect demands simultaneous success at the same endpoint cycle, but c misses at C91.

Why candidates get it wrong

Engineers may glance at c=1 at C92 and incorrectly assume delayed recovery is acceptable.

Interviewer follow-up

What operator would allow b and c to complete on different endpoints from the same start?

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