Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
      • disable iff Abort Semantics
      • Multiclock Ack Visibility
      • Vacuity Hidden by Mode Gating
      • throughout Glitch Before Completion
      • within Timeout Window Escape
      • Intersect Requirement in Dual Checks
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
Loading lesson

‹Assertion Debug Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Assertion Debug Puzzles
  5. Vacuity Hidden by Mode Gating

VLSI DV Interview Puzzles · All levels

Vacuity Hidden by Mode Gating

Property intent: functional req must get gnt in up to 2 cycles. Timeline: req pulses at C60 and C66, but scan_mode=1 on both cycles; gnt never asserts. Determine the verdict.

On this page

    Puzzle

    Difficulty: Medium · Puzzle 3 of 6 · Topic: Assertion Debug Puzzles

    Property intent: functional req must get gnt in up to 2 cycles. Timeline: req pulses at C60 and C66, but scan_mode=1 on both cycles; gnt never asserts. Determine the verdict.

    Code

    design.sv
    property p_mode_gated_req;
      @(posedge clk) (req && !scan_mode) |-> ##[0:2] gnt;
    endproperty

    Hint

    Check whether antecedent is ever true in sampled cycles.

    Step-by-step solution

    Diagram
    1) req is present, but scan_mode=1 each time req is high.
    2) Antecedent req && !scan_mode is never true.
    3) No checking thread is spawned.

    Answer

    Answer: VACUOUS-PASS - all req pulses are masked out of the antecedent, so no functional grant obligation is actually checked.

    Why candidates get it wrong

    Teams may celebrate green assertions while completely missing functional traffic due to over-gated antecedents.

    Interviewer follow-up

    What extra assertion or cover would you add to guarantee non-scan req activity is exercised?

    Related topics

    • Back to Assertion Debug Puzzles

    • SVA Assertion Puzzles section

    Previous

    125 / 210

    Next: throughout Glitch Before Completion

    Up next

    Up nextthroughout Glitch Before Completion

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • disable iff Abort Semantics
    • within Timeout Window Escape
    • Intersect Requirement in Dual Checks