VLSI DV Interview Puzzles · All levels
Assertion Debug Puzzles
Debugging real assertion failures and false confidence from reset masking, multiclock sampling, and vacuous threads.
About this puzzle set
Debugging real assertion failures and false confidence from reset masking, multiclock sampling, and vacuous threads.
Puzzles in this topic
diagram
1. disable iff Abort Semantics [Medium]
2. Multiclock Ack Visibility [Hard]
3. Vacuity Hidden by Mode Gating [Medium]
4. throughout Glitch Before Completion [Hard]
5. within Timeout Window Escape [Hard]
6. Intersect Requirement in Dual Checks [Medium]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.