VLSI DV Interview Puzzles · All levels

Vector $rose Sampling Trap

Property intent: on $rose(state[3:0]), enter must assert. Timeline: state changes from 4'b0010 at C100 to 4'b0100 at C101, enter=0 at C101. Determine the verdict.

Puzzle

Difficulty: Hard · Puzzle 6 of 6 · Topic: Temporal Corner Puzzles

Property intent: on $rose(state[3:0]), enter must assert. Timeline: state changes from 4'b0010 at C100 to 4'b0100 at C101, enter=0 at C101. Determine the verdict.

Code

systemverilog

property p_vector_rose;
  @(posedge clk) $rose(state[3:0]) |-> enter;
endproperty

Hint

In SVA, $rose on a vector expression is based on the least significant bit transition.

Step-by-step solution

diagram

1) LSB of state is 0 at C100 and 0 at C101.
2) $rose(state[3:0]) is therefore false at C101, despite upper-bit toggles.
3) Antecedent does not trigger; consequent is not checked.

Answer

Answer: VACUOUS-PASS - no antecedent trigger occurs because the vector LSB did not rise, so implication passes vacuously.

Why candidates get it wrong

Interviewers use this to catch assumptions that $rose(vector) means any-bit rise.

Interviewer follow-up

How would you rewrite the trigger to detect a rise on any bit of state?

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