VLSI DV Interview Puzzles · All levels

$rose Sampled on Clock Edge

Property intent: after start rises, done must be high one cycle later. Timeline: at C40 sample, start observed as 0->1 transition; C41 d1. Determine the verdict.

Puzzle

Difficulty: Easy · Puzzle 2 of 6 · Topic: Temporal Corner Puzzles

Property intent: after start rises, done must be high one cycle later. Timeline: at C40 sample, start observed as 0->1 transition; C41 done=1. Determine the verdict.

Code

systemverilog

property p_rose_delay;
  @(posedge clk) $rose(start) |-> ##1 done;
endproperty

Hint

$rose checks sampled previous value versus current sampled value.

Step-by-step solution

diagram

1) $rose(start) is true at C40, so implication triggers.
2) ##1 done requires done at C41.
3) done is high at C41.

Answer

Answer: PASS - sampled rise is detected at C40 and the one-cycle-later done requirement is met.

Why candidates get it wrong

Many answers confuse asynchronous transition time with sampled assertion semantics.

Interviewer follow-up

If done were high at C40 but low at C41, would this still pass?

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