VLSI DV Interview Puzzles · All levels

$fell With Non-Overlapped Consequent

Property intent: when valid falls, idle must be high on the next cycle. Timeline: valid falls at C70, idle=1 at C70, idle=0 at C71. Determine the verdict.

Puzzle

Difficulty: Medium · Puzzle 3 of 6 · Topic: Temporal Corner Puzzles

Property intent: when valid falls, idle must be high on the next cycle. Timeline: valid falls at C70, idle=1 at C70, idle=0 at C71. Determine the verdict.

Code

systemverilog

property p_fell_idle;
  @(posedge clk) $fell(valid) |=> idle;
endproperty

Hint

Non-overlapped implication checks idle one cycle after the fall event.

Step-by-step solution

diagram

1) $fell(valid) is true at C70.
2) |=> shifts consequent sampling to C71.
3) idle is 0 at C71, violating requirement.

Answer

Answer: FAIL - idle is not high on the required post-fall cycle.

Why candidates get it wrong

Candidates often see idle high at the fall cycle and mistakenly declare pass.

Interviewer follow-up

What operator change would make the same waveform pass without changing signals?

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