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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
    • Temporal Corner Puzzles
      • $past Startup History Hole
      • $rose Sampled on Clock Edge
      • $fell With Non-Overlapped Consequent
      • $stable Repeated Hold Check
      • Cross-Cycle Correlation With $past Depth
      • Vector $rose Sampling Trap
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Temporal Corner Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Temporal Corner Puzzles
  5. $fell With Non-Overlapped Consequent

VLSI DV Interview Puzzles · All levels

$fell With Non-Overlapped Consequent

Property intent: when valid falls, idle must be high on the next cycle. Timeline: valid falls at C70, idle=1 at C70, idle=0 at C71. Determine the verdict.

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    Puzzle

    Difficulty: Medium · Puzzle 3 of 6 · Topic: Temporal Corner Puzzles

    Property intent: when valid falls, idle must be high on the next cycle. Timeline: valid falls at C70, idle=1 at C70, idle=0 at C71. Determine the verdict.

    Code

    design.sv
    property p_fell_idle;
      @(posedge clk) $fell(valid) |=> idle;
    endproperty

    Hint

    Non-overlapped implication checks idle one cycle after the fall event.

    Step-by-step solution

    Diagram
    1) $fell(valid) is true at C70.
    2) |=> shifts consequent sampling to C71.
    3) idle is 0 at C71, violating requirement.

    Answer

    Answer: FAIL - idle is not high on the required post-fall cycle.

    Why candidates get it wrong

    Candidates often see idle high at the fall cycle and mistakenly declare pass.

    Interviewer follow-up

    What operator change would make the same waveform pass without changing signals?

    Related topics

    • Back to Temporal Corner Puzzles

    • SVA Assertion Puzzles section

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    See also

    • $past Startup History Hole
    • Cross-Cycle Correlation With $past Depth
    • Vector $rose Sampling Trap