VLSI DV Interview Puzzles · All levels

$stable Repeated Hold Check

Property intent: after cfg_update, cfg_bus must remain stable for two cycles. Timeline: C80 cfg_update=1, C81 cfg_bus=16'h1234, C82 cfg_bus=16'h1234. Determine the verdict.

Puzzle

Difficulty: Medium · Puzzle 4 of 6 · Topic: Temporal Corner Puzzles

Property intent: after cfg_update, cfg_bus must remain stable for two cycles. Timeline: C80 cfg_update=1, C81 cfg_bus=16'h1234, C82 cfg_bus=16'h1234. Determine the verdict.

Code

systemverilog

property p_cfg_stable;
  @(posedge clk) cfg_update |=> $stable(cfg_bus)[*2];
endproperty

Hint

Count how many consecutive cycles satisfy $stable after the non-overlapped shift.

Step-by-step solution

diagram

1) cfg_update at C80 triggers non-overlapped check starting C81.
2) $stable(cfg_bus) is true at C81 and C82 for same sampled value.
3) [*2] requires exactly two consecutive true evaluations and is met.

Answer

Answer: PASS - cfg_bus remains stable for the required two consecutive post-update samples.

Why candidates get it wrong

A common mistake is evaluating stability on C80 immediately despite |=>.

Interviewer follow-up

If cfg_bus changed at C82, which repetition element would fail?

Navigate