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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
    • Temporal Corner Puzzles
      • $past Startup History Hole
      • $rose Sampled on Clock Edge
      • $fell With Non-Overlapped Consequent
      • $stable Repeated Hold Check
      • Cross-Cycle Correlation With $past Depth
      • Vector $rose Sampling Trap
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Temporal Corner Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Temporal Corner Puzzles
  5. $stable Repeated Hold Check

VLSI DV Interview Puzzles · All levels

$stable Repeated Hold Check

Property intent: after cfg_update, cfg_bus must remain stable for two cycles. Timeline: C80 cfg_update=1, C81 cfg_bus=16'h1234, C82 cfg_bus=16'h1234. Determine the verdict.

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    Puzzle

    Difficulty: Medium · Puzzle 4 of 6 · Topic: Temporal Corner Puzzles

    Property intent: after cfg_update, cfg_bus must remain stable for two cycles. Timeline: C80 cfg_update=1, C81 cfg_bus=16'h1234, C82 cfg_bus=16'h1234. Determine the verdict.

    Code

    design.sv
    property p_cfg_stable;
      @(posedge clk) cfg_update |=> $stable(cfg_bus)[*2];
    endproperty

    Hint

    Count how many consecutive cycles satisfy $stable after the non-overlapped shift.

    Step-by-step solution

    Diagram
    1) cfg_update at C80 triggers non-overlapped check starting C81.
    2) $stable(cfg_bus) is true at C81 and C82 for same sampled value.
    3) [*2] requires exactly two consecutive true evaluations and is met.

    Answer

    Answer: PASS - cfg_bus remains stable for the required two consecutive post-update samples.

    Why candidates get it wrong

    A common mistake is evaluating stability on C80 immediately despite |=>.

    Interviewer follow-up

    If cfg_bus changed at C82, which repetition element would fail?

    Related topics

    • Back to Temporal Corner Puzzles

    • SVA Assertion Puzzles section

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    Next: Cross-Cycle Correlation With $past Depth

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    Up nextCross-Cycle Correlation With $past Depth

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    See also

    • $past Startup History Hole
    • $rose Sampled on Clock Edge
    • Vector $rose Sampling Trap