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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
    • Temporal Corner Puzzles
      • $past Startup History Hole
      • $rose Sampled on Clock Edge
      • $fell With Non-Overlapped Consequent
      • $stable Repeated Hold Check
      • Cross-Cycle Correlation With $past Depth
      • Vector $rose Sampling Trap
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹SVA Assertion Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Temporal Corner Puzzles

VLSI DV Interview Puzzles · All levels

Temporal Corner Puzzles

Sampled-value functions and timing history pitfalls involving $past, $rose, $fell, and $stable.

  • 6topics
  • 6lessons

Topics in this section

  1. 1$past Startup History Hole1 lesson
  2. 2$rose Sampled on Clock Edge1 lesson
  3. 3$fell With Non-Overlapped Consequent1 lesson
  4. 4$stable Repeated Hold Check1 lesson
  5. 5Cross-Cycle Correlation With $past Depth1 lesson
  6. 6Vector $rose Sampling Trap1 lesson
On this page

    About this puzzle set

    Sampled-value functions and timing history pitfalls involving $past, $rose, $fell, and $stable.

    Puzzles in this topic

    Diagram
    1. $past Startup History Hole  [Medium]
    2. $rose Sampled on Clock Edge  [Easy]
    3. $fell With Non-Overlapped Consequent  [Medium]
    4. $stable Repeated Hold Check  [Medium]
    5. Cross-Cycle Correlation With $past Depth  [Hard]
    6. Vector $rose Sampling Trap  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    Related topics

    • SVA Assertion Puzzles section

    • VLSI DV Interview Puzzles hub

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    See also

    • Sequence Puzzles
    • Implication Puzzles
    • Assertion Debug Puzzles