VLSI DV Interview Puzzles · All levels

within Timeout Window Escape

Property intent: ack ##1 done must complete inside req-to-timeout window. Timeline: C80 start=1 req=1, C82 ack=1, C83 timeout=1, C84 d1. Determine the verdict.

Puzzle

Difficulty: Hard · Puzzle 5 of 6 · Topic: Assertion Debug Puzzles

Property intent: ack ##1 done must complete inside req-to-timeout window. Timeline: C80 start=1 req=1, C82 ack=1, C83 timeout=1, C84 done=1. Determine the verdict.

Code

systemverilog

sequence timeout_window;
  req ##[1:3] timeout;
endsequence

sequence rsp_pair;
  ack ##1 done;
endsequence

property p_rsp_within_timeout;
  @(posedge clk) start |-> (rsp_pair within timeout_window);
endproperty

Hint

within requires the entire rsp_pair sequence to be enclosed by timeout_window.

Step-by-step solution

diagram

1) timeout_window can match from C80 to C83.
2) rsp_pair spans C82 to C84.
3) done at C84 falls outside the matched timeout window end at C83.
4) Containment fails.

Answer

Answer: FAIL - the response starts inside the window but finishes after timeout, violating within containment.

Why candidates get it wrong

A classic review bug is checking only ack timing and ignoring full-sequence completion bounds.

Interviewer follow-up

How would you rewrite this if partial overlap (not full containment) were acceptable?

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