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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
      • disable iff Abort Semantics
      • Multiclock Ack Visibility
      • Vacuity Hidden by Mode Gating
      • throughout Glitch Before Completion
      • within Timeout Window Escape
      • Intersect Requirement in Dual Checks
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Assertion Debug Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Assertion Debug Puzzles
  5. within Timeout Window Escape

VLSI DV Interview Puzzles · All levels

within Timeout Window Escape

Property intent: ack ##1 done must complete inside req-to-timeout window. Timeline: C80 start=1 req=1, C82 ack=1, C83 timeout=1, C84 d1. Determine the verdict.

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    Puzzle

    Difficulty: Hard · Puzzle 5 of 6 · Topic: Assertion Debug Puzzles

    Property intent: ack ##1 done must complete inside req-to-timeout window. Timeline: C80 start=1 req=1, C82 ack=1, C83 timeout=1, C84 done=1. Determine the verdict.

    Code

    design.sv
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    sequence timeout_window;
      req ##[1:3] timeout;
    endsequence
    
    sequence rsp_pair;
      ack ##1 done;
    endsequence
    
    property p_rsp_within_timeout;
      @(posedge clk) start |-> (rsp_pair within timeout_window);
    endproperty

    Hint

    within requires the entire rsp_pair sequence to be enclosed by timeout_window.

    Step-by-step solution

    Diagram
    1) timeout_window can match from C80 to C83.
    2) rsp_pair spans C82 to C84.
    3) done at C84 falls outside the matched timeout window end at C83.
    4) Containment fails.

    Answer

    Answer: FAIL - the response starts inside the window but finishes after timeout, violating within containment.

    Why candidates get it wrong

    A classic review bug is checking only ack timing and ignoring full-sequence completion bounds.

    Interviewer follow-up

    How would you rewrite this if partial overlap (not full containment) were acceptable?

    Related topics

    • Back to Assertion Debug Puzzles

    • SVA Assertion Puzzles section

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    See also

    • disable iff Abort Semantics
    • Multiclock Ack Visibility
    • Vacuity Hidden by Mode Gating