VLSI DV Interview Puzzles · All levels

throughout Glitch Before Completion

Property intent: once start happens, valid must remain high throughout the done-arrival window (1 to 3 cycles). Timeline: C70 start=1 valid=1, C71 valid=1, C72 valid=0, C73 d1. Determine the verdict.

Puzzle

Difficulty: Hard · Puzzle 4 of 6 · Topic: Assertion Debug Puzzles

Property intent: once start happens, valid must remain high throughout the done-arrival window (1 to 3 cycles). Timeline: C70 start=1 valid=1, C71 valid=1, C72 valid=0, C73 done=1. Determine the verdict.

Code

systemverilog

property p_valid_throughout_wait;
  @(posedge clk) start |-> valid throughout (##[1:3] done);
endproperty

Hint

A single-cycle valid glitch inside the chosen window is enough to fail throughout.

Step-by-step solution

diagram

1) start at C70 triggers consequent.
2) done matches via ##3 at C73.
3) valid must hold continuously over the matched wait interval.
4) valid is 0 at C72, violating throughout before done arrives.

Answer

Answer: FAIL - valid drops during the active wait window, so throughout constraint is broken.

Why candidates get it wrong

Debuggers often inspect only the done cycle and miss mid-window validity glitches.

Interviewer follow-up

If done occurred at C71 instead, would the same valid waveform still fail?

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