Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
      • disable iff Abort Semantics
      • Multiclock Ack Visibility
      • Vacuity Hidden by Mode Gating
      • throughout Glitch Before Completion
      • within Timeout Window Escape
      • Intersect Requirement in Dual Checks
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
Loading lesson

‹Assertion Debug Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Assertion Debug Puzzles
  5. disable iff Abort Semantics

VLSI DV Interview Puzzles · All levels

disable iff Abort Semantics

Property intent: after req, gnt must arrive within 1 to 2 cycles, except when reset is active. Timeline: C50 req=1 and rst_n=1, C51 rst_n=0, C52 rst_n=0 gnt=0, C53 rst_n=1. Determine the verdict for the C50 attempt.

On this page

    Puzzle

    Difficulty: Medium · Puzzle 1 of 6 · Topic: Assertion Debug Puzzles

    Property intent: after req, gnt must arrive within 1 to 2 cycles, except when reset is active. Timeline: C50 req=1 and rst_n=1, C51 rst_n=0, C52 rst_n=0 gnt=0, C53 rst_n=1. Determine the verdict for the C50 attempt.

    Code

    design.sv
    property p_disable_abort;
      @(posedge clk) disable iff (!rst_n) req |-> ##[1:2] gnt;
    endproperty

    Hint

    Check what happens to in-flight threads when disable iff becomes true.

    Step-by-step solution

    Diagram
    1) req at C50 starts a checking thread.
    2) rst_n goes low at C51, making disable iff condition true.
    3) Active thread is aborted (discarded) immediately.
    4) Aborted thread does not report fail for missing gnt.

    Answer

    Answer: VACUOUS-PASS - the in-flight obligation is aborted by disable iff, so no failure is reported for that attempt.

    Why candidates get it wrong

    Debug sessions often misclassify aborted threads as hidden fails, leading to wrong RTL fixes.

    Interviewer follow-up

    What property pattern would you use if reset should cause an explicit failure instead of abort?

    Related topics

    • Back to Assertion Debug Puzzles

    • SVA Assertion Puzzles section

    Previous

    123 / 210

    Next: Multiclock Ack Visibility

    Up next

    Up nextMulticlock Ack Visibility

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Vacuity Hidden by Mode Gating
    • throughout Glitch Before Completion
    • within Timeout Window Escape