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Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
    • Global and Detailed Routing Convergence
    • Antenna Rules and Corrective Strategies
    • Metal Layer Planning and Capacity Management
    • Shielding, Tie Cells, and Signal Hygiene
    • Via Planning and Via Ladder Reliability
    • Route-Driven Timing Optimization
    • Special Nets and Power Routing Strategy
    • Routing DRC Debug and Forensic Workflow
    • Routing Tricky Q&A
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
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‹Routing
  1. Topics
  2. Physical Design
  3. Routing
  4. Routing Tricky Q&A

Physical Design · All levels

Routing Tricky Q&A

20+ senior Routing interview questions.

On this page

    Q&A bank

    Answer with mechanism, pitfall, regression check, and release judgment. At 10+ years, a correct definition is not enough.

    Senior answer rubric

    1. Start with the failing metric and analysis context.

    2. Explain the physical or constraint mechanism.

    3. Name the cheapest evidence-gathering experiment.

    4. Choose a bounded fix and state what it can regress.

    5. Close with signoff, waiver, or escalation criteria.

    What metric best predicts detailed-route pain early?

    Diagram
    [INT][PD]
    
    Q: What metric best predicts detailed-route pain early?
    
    A:
    Persistent global overflow clusters that survive incremental placement/route guide tuning.
    
    FOLLOW-UP TRAP: Waiting for full detailed route to discover capacity issues.

    Why should DRC be tracked by class, not only total count?

    Diagram
    [INT][PD]
    
    Q: Why should DRC be tracked by class, not only total count?
    
    A:
    Class trends identify systemic causes and proper fix strategies; totals hide critical patterns.
    
    FOLLOW-UP TRAP: Declaring progress from small total-count drops.

    How do antenna fixes impact timing?

    Diagram
    [INT][PD]
    
    Q: How do antenna fixes impact timing?
    
    A:
    Diodes and reroutes can alter capacitance and delay, so post-fix extraction is mandatory.
    
    FOLLOW-UP TRAP: Assuming antenna fixes are timing-neutral.

    When is layer promotion the right timing fix?

    Diagram
    [INT][PD]
    
    Q: When is layer promotion the right timing fix?
    
    A:
    When delay is wire-dominant and upper-layer capacity is available without severe congestion side effects.
    
    FOLLOW-UP TRAP: Promoting nets without RC diagnosis.

    What is a strong signal that via planning is insufficient?

    Diagram
    [INT][PD]
    
    Q: What is a strong signal that via planning is insufficient?
    
    A:
    Recurring via-related EM hotspots and high single-cut usage on high-current nets.
    
    FOLLOW-UP TRAP: Relying only on DRC-clean status.

    How do shielding decisions affect routability?

    Diagram
    [INT][PD]
    
    Q: How do shielding decisions affect routability?
    
    A:
    Shielding consumes routing tracks; targeted application is required to avoid congestion inflation.
    
    FOLLOW-UP TRAP: Assuming shielding cost is negligible.

    Why do special nets need separate review gates?

    Diagram
    [INT][PD]
    
    Q: Why do special nets need separate review gates?
    
    A:
    They carry higher reliability and integrity risk than ordinary signals and can fail despite general route health.
    
    FOLLOW-UP TRAP: Treating them as normal data nets.

    How should you triage thousands of DRC violations quickly?

    Diagram
    [INT][PD]
    
    Q: How should you triage thousands of DRC violations quickly?
    
    A:
    Rank by class/severity/systemic origin, fix high-impact generators first, then clean residuals.
    
    FOLLOW-UP TRAP: Manual one-by-one triage.

    What indicates routing ECO churn is too high?

    Diagram
    [INT][PD]
    
    Q: What indicates routing ECO churn is too high?
    
    A:
    Violation classes move between regions without net reduction and timing/extraction become unstable between iterations.
    
    FOLLOW-UP TRAP: Continuing the same recipe indefinitely.

    How do you prove routing improvements are real?

    Diagram
    [INT][PD]
    
    Q: How do you prove routing improvements are real?
    
    A:
    Show class-wise DRC reduction, overflow improvement, and stable or improved extracted timing.
    
    FOLLOW-UP TRAP: Using GUI snapshots without report deltas.

    Why can post-route WNS collapse despite clean pre-route timing?

    Diagram
    [INT][PD]
    
    Q: Why can post-route WNS collapse despite clean pre-route timing?
    
    A:
    Extracted RC and coupling effects reveal interconnect delays not captured in pre-route estimates.
    
    FOLLOW-UP TRAP: Blaming STA setup only.

    How do you prevent route-driven timing fixes from creating new DRC?

    Diagram
    [INT][PD]
    
    Q: How do you prevent route-driven timing fixes from creating new DRC?
    
    A:
    Use bounded ECO regions, rule-aware fix recipes, and immediate class-wise DRC regression checks.
    
    FOLLOW-UP TRAP: Running unconstrained global optimization passes.

    What is the role of jog/detour metrics in route analysis?

    Diagram
    [INT][PD]
    
    Q: What is the role of jog/detour metrics in route analysis?
    
    A:
    They expose inefficient topology and layer-policy conflicts that degrade delay and manufacturability.
    
    FOLLOW-UP TRAP: Ignoring geometry quality when connectivity exists.

    When should placement be revisited during routing?

    Diagram
    [INT][PD]
    
    Q: When should placement be revisited during routing?
    
    A:
    When overflow and DRC remain structurally tied to capacity/geometry limits that route-level tuning cannot resolve.
    
    FOLLOW-UP TRAP: Forcing routing-only closure on structural congestion.

    How do tie-cell issues surface during routing signoff?

    Diagram
    [INT][PD]
    
    Q: How do tie-cell issues surface during routing signoff?
    
    A:
    Floating input and LVS/precheck violations appear, often coupled with unreliable logic behavior risk.
    
    FOLLOW-UP TRAP: Assuming tie-cell mistakes are synthesis-only.

    Why is route recipe traceability critical for DRC closure?

    Diagram
    [INT][PD]
    
    Q: Why is route recipe traceability critical for DRC closure?
    
    A:
    It enables causal debugging and reproducible convergence across runs.
    
    FOLLOW-UP TRAP: Changing many knobs without logging.

    How do you choose between reroute and waiver for residual DRC?

    Diagram
    [INT][PD]
    
    Q: How do you choose between reroute and waiver for residual DRC?
    
    A:
    Assess rule severity, manufacturability impact, and waiver policy; reroute critical classes whenever feasible.
    
    FOLLOW-UP TRAP: Waiving by count pressure alone.

    What minimum artifacts belong in a routing signoff packet?

    Diagram
    [INT][PD]
    
    Q: What minimum artifacts belong in a routing signoff packet?
    
    A:
    DRC class report, overflow summary, extraction-based STA, EM/IR evidence, and ECO/change log.
    
    FOLLOW-UP TRAP: Submitting only timing numbers.

    How do power routing defects affect timing teams indirectly?

    Diagram
    [INT][PD]
    
    Q: How do power routing defects affect timing teams indirectly?
    
    A:
    IR-drop hotspots alter cell delay behavior, causing path instability and corner surprises.
    
    FOLLOW-UP TRAP: Treating power and timing as independent.

    How should you narrate routing closure in an interview?

    Diagram
    [INT][PD]
    
    Q: How should you narrate routing closure in an interview?
    
    A:
    Explain class-based triage, systemic fixes, extraction validation, and quantified regression control.
    
    FOLLOW-UP TRAP: Describing only tool command sequence.

    How to drill this Q&A bank

    Use each question as a two-minute mock. The target answer is not an essay; it is a structured closure response with a metric, mechanism, risk, and follow-up check.

    Answer template

    Diagram
    MECHANISM: what physical effect or tool step is involved
    WHEN: where it appears in the flow
    PITFALL: one wrong junior answer
    CHECK: report/map/checklist item that proves the answer

    Scoring

    • 5/5: metric, mechanism, experiment, regression, and release decision named without prompting.

    • 4/5: technically correct and names regression, but misses ownership or escalation criteria.

    • 3/5: correct concept but no decision framework.

    • 1/5: tool command or buzzword with no mechanism.

    Principal-level review bar

    Q&A bank pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Routing decides whether the placed design is manufacturable and extractable. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

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    See also

    • Global and Detailed Routing Convergence
    • Antenna Rules and Corrective Strategies
    • Metal Layer Planning and Capacity Management