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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
    • Protocols Whiteboard Framework
    • Scenario: AXI Ordering Trap
    • Scenario: DDR Bandwidth Collapse
    • Scenario: PCIe Link Degrade
    • Protocols Interview Q&A Bank
  • Interface Protocols Cheatsheet
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‹Protocols Interview Prep
  1. Topics
  2. Bus Protocols
  3. Protocols Interview Prep
  4. Protocols Whiteboard Framework

Interface Protocols · All levels

Protocols Whiteboard Framework

A reusable structure for protocol architecture and debug interviews.

On this page

    Protocol whiteboard flow

    Diagram
    1. Draw the layers: software, transaction, link/channel, physical/timing.
    2. Draw the transaction identity: ID, tag, address, endpoint, lane, or cache line.
    3. Mark flow control: ready, grant, credit, FIFO, retry, or link state.
    4. Mark ordering: same ID, different ID, barrier, fence, completion, or shareability.
    5. State the metric: latency, throughput, error rate, retry, or training margin.
    6. State the artifact: waveform, VIP log, analyzer trace, firmware log, or counter.
    7. Propose one reduced experiment and one product regression.

    Key takeaways

    • The best protocol answers are layered, measurable, and tied to a specific transaction.

    • Never answer with only a block diagram; carry the failing transaction through the diagram.

    Protocol deep dive

    Protocol correctness is a layered contract enforced at every boundary.

    Concept diagram

    Diagram
    intent -> transaction -> channel -> physical

    Metric graph

    Diagram
    baseline -> experiment -> target

    Metrics and artifacts to collect

    • latency

    • throughput

    • error rate

    • compliance status

    Mini case study

    Always anchor debug to the first bad transaction.

    Debug branches

    • Name layer

    • Name ID

    • Name artifact

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    PreviousNext: Scenario: AXI Ordering Trap

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    Up nextScenario: AXI Ordering Trap

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    See also

    • Scenario: DDR Bandwidth Collapse
    • Scenario: PCIe Link Degrade
    • Protocols Interview Q&A Bank