Interface Protocols · All levels
Scenario: AXI Ordering Trap
A DMA engine passes single-ID tests but fails when traffic uses multiple IDs and a width converter sits between the master and interconnect.
Scenario
A DMA engine passes single-ID tests but fails when traffic uses multiple IDs and a width converter sits between the master and interconnect.
OBSERVED METRIC
random data corruption after enabling multiple outstanding IDs
45-MINUTE INTERVIEW FLOW
0-5: clarify protocol, layer, and traffic setup
5-15: draw transaction flow and ownership
15-25: isolate first bad transaction or stalled progress
25-35: propose reduced experiment and fix options
35-45: state compliance, workload, and regression planCommon pitfalls
Assume AXI preserves all order
Ignore bridge ID remap
Debug only data channel
Scenario debrief
Score the answer: layer, transaction ID, metric, artifact, regression.
Reference stack
intent -> transaction -> channel -> physicalMetric pattern
baseline -> experiment -> targetDebrief prompts
Which protocol layer did you name first?
Which transaction identity did you carry through the story?
What reduced experiment did you propose?
What compliance and product regressions did you list?
Key takeaways
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Common pitfalls
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.