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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
    • VIP & Agent Architecture
    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan
    • Protocol Waveform Debug
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Protocol Verification & Compliance
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. Protocol Verification & Compliance: Tricky Q&A

Interface Protocols · All levels

Protocol Verification & Compliance: Tricky Q&A

Senior interview and review questions for Protocol Verification & Compliance.

On this page

    Section Q&A bank

    Use these drills after completing all topics in Protocol Verification & Compliance. Answer with layer, transaction, metric, artifact, and regression.

    Scoreboard vs assertion — division of labor?

    Diagram
    [INT][PROT][PROTOCOL-VERIFICATION]
    
    Q: Scoreboard vs assertion — division of labor?
    
    A:
    Assertions check local temporal rules; scoreboards correlate end-to-end request/response pairs.
    
    FOLLOW-UP TRAP: Assertions alone proving system correctness.

    What is a compliance gap?

    Diagram
    [INT][PROT][PROTOCOL-VERIFICATION]
    
    Q: What is a compliance gap?
    
    A:
    Spec requirement with no mapped test, assertion, or coverage bin.
    
    FOLLOW-UP TRAP: Closing coverage % without requirement trace.

    VIP pass but chip fails — why?

    Diagram
    [INT][PROT][PROTOCOL-VERIFICATION]
    
    Q: VIP pass but chip fails — why?
    
    A:
    Integration assumptions: address map, reset, clock, bridge, or firmware differ from block env.
    
    FOLLOW-UP TRAP: Closing the bug as 'VIP issue'.

    Q&A drill guide

    Diagram
    LAYER -> TRANSACTION -> METRIC -> ARTIFACT -> FIX -> REGRESSION

    Sketch while answering

    Diagram
    VERIFICATION CLOSURE LOOP
    
    spec clause -> test -> assertion -> coverage -> waiver -> signoff
                      ^                           |
                      +--------- gap found --------+

    Common traps

    • If VIP pass but silicon fail, check integration assumptions.

    • If scoreboard noisy, fix key (ID+port+addr).

    • If coverage plateau, add compliance gap analysis not more repeats.

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    PreviousNext: Protocols Interview Prep

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    Up nextProtocols Interview Prep

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    See also

    • VIP & Agent Architecture
    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan