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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
    • VIP & Agent Architecture
      • VIP & Agent Architecture: Mechanism
      • VIP & Agent Architecture: Inputs & Outputs
      • VIP & Agent Architecture: Reports & Metrics
      • VIP & Agent Architecture: Debug Playbook
      • VIP & Agent Architecture: Worked Example
      • VIP & Agent Architecture: Pitfalls & Red Flags
      • VIP & Agent Architecture: Interview Drills
      • VIP & Agent Architecture: Review Checklist
      • VIP & Agent Architecture: Theory Deep Dive
      • VIP & Agent Architecture: Design Space
      • VIP & Agent Architecture: Expanded Case Study
      • VIP & Agent Architecture: Step-by-Step Walkthrough
      • VIP & Agent Architecture: Comparison Matrix
      • VIP & Agent Architecture: Software / Programmer View
      • VIP & Agent Architecture: Silicon PPA Impact
    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan
    • Protocol Waveform Debug
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Protocol Verification & Compliance
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. VIP & Agent Architecture

Interface Protocols · All levels

VIP & Agent Architecture

Protocol Verification & Compliance: VIP separates driver, monitor, sequencer, checker, and coverage so protocol intent is observable and reusable.

  • 15topics
  • 15lessons

Topics in this section

  1. 1VIP & Agent Architecture: Mechanism1 lesson
  2. 2VIP & Agent Architecture: Inputs & Outputs1 lesson
  3. 3VIP & Agent Architecture: Reports & Metrics1 lesson
  4. 4VIP & Agent Architecture: Debug Playbook1 lesson
  5. 5VIP & Agent Architecture: Worked Example1 lesson
  6. 6VIP & Agent Architecture: Pitfalls & Red Flags1 lesson
  7. 7VIP & Agent Architecture: Interview Drills1 lesson
  8. 8VIP & Agent Architecture: Review Checklist1 lesson
  9. 9VIP & Agent Architecture: Theory Deep Dive1 lesson
  10. 10VIP & Agent Architecture: Design Space1 lesson
  11. 11VIP & Agent Architecture: Expanded Case Study1 lesson
  12. 12VIP & Agent Architecture: Step-by-Step Walkthrough1 lesson
  13. 13VIP & Agent Architecture: Comparison Matrix1 lesson
  14. 14VIP & Agent Architecture: Software / Programmer View1 lesson
  15. 15VIP & Agent Architecture: Silicon PPA Impact1 lesson
On this page

    What this topic teaches

    VIP & Agent Architecture is about converting a protocol rule into a measurable silicon contract. VIP separates driver, monitor, sequencer, checker, and coverage so protocol intent is observable and reusable. The hard part is never the happy-path diagram; it is proving, under real traffic, which layer and which transaction broke the contract.

    The senior-engineer question

    When stimulus coverage, monitor mismatch rate, illegal sequence detection moves, can you identify the transaction, the protocol layer, the responsible owner, and the smallest experiment that proves the root cause?

    Diagram
    PROTOCOL STACK VIEW — VIP & Agent Architecture
    
    software / firmware intent
            |
            v
    transaction semantics: address, ID, length, attributes, ordering
            |
            v
    link / channel behavior: handshake, credits, backpressure, retries
            |
            v
    physical or timing layer: clocking, reset, pins, lanes, PHY
            |
            v
    observability: waveform, VIP transaction, counter, analyzer trace
    
    Debug rule: never jump layers without carrying the transaction identity with you.

    Picture the protocol

    Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.

    UVM-style protocol agent

    Diagram
    PROTOCOL AGENT
    
      sequencer --> driver --> [ DUT pins ]
                                  |
      monitor <-------------------+
         |
         +--> scoreboard (expected vs actual)
         +--> coverage   (which scenarios were hit)
    
    Active agent drives; passive agent only observes (for system reuse).

    Transaction sequence

    Diagram
    SEQUENCE — VIP & Agent Architecture
    
      initiator            interconnect/PHY            target
          |  request (id) ------->  |                     |
          |                         |  forward ----------> |
          |                         |                     | work
          |                         |  <---- response ---- |
          |  <----- complete ------ |                     |
          |
       metric captured here: stimulus coverage, monitor mismatch rate, illegal sequence detection

    Who owns which layer

    Diagram
    LAYER RESPONSIBILITY — VIP & Agent Architecture
    
    layer          owns                         common failure
    -----------    --------------------------   -----------------------
    software       intent, ordering needs       wrong assumption
    transaction    id/addr/len/attributes       ordering / outstanding
    link/channel   handshake, credits, retry    backpressure / deadlock
    physical       clock/reset/lanes/PHY        timing / training / SI
    observability  waveform/log/counter         missing evidence

    Evidence to collect

    • Primary metric: stimulus coverage, monitor mismatch rate, illegal sequence detection.

    • Primary artifact: UVM agent diagram, monitor transaction log, checker failure.

    • Owners to bring into review: verification lead, VIP owner, RTL owner.

    • Spec clause or requirement ID for every claim.

    • One traffic replay that fails and one reduced sequence that isolates the rule.

    Ownership map

    Diagram
    OWNERSHIP MAP — VIP & Agent Architecture
    
    evidence type        owner who reads it
    -----------------    ---------------------------
    waveform/RTL        verification lead
    spec/VIP            VIP owner
    firmware/system     RTL owner
    
    Rule: every metric must have a named owner before a review starts.

    Subpages in this topic

    Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

    Key takeaways

    • Carry transaction identity across waveform, log, counter, and spec view.

    • Separate protocol violation, integration configuration, and performance bottleneck before proposing a fix.

    • Draw the diagram first; the waveform should confirm the picture, not replace it.

    Common pitfalls

    • Debugging only one channel or layer.

    • Treating a VIP error message as root cause instead of evidence.

    • Quoting peak interface bandwidth without payload efficiency.

    Protocol deep dive

    Verification closes the gap between 'works in directed test' and 'legal under all stressed traffic'.

    Concept diagram

    Diagram
    VERIFICATION CLOSURE LOOP
    
    spec clause -> test -> assertion -> coverage -> waiver -> signoff
                      ^                           |
                      +--------- gap found --------+

    Metric graph

    Diagram
    COVERAGE vs ESCAPE RATE
    
    escapes
      |*
      | *
      |  *
      |   **  <- knee: more random helps
      |     ****
      +----------------> constrained-random depth

    Metrics and artifacts to collect

    • compliance pass rate

    • coverage closure

    • scoreboard mismatch rate

    • assertion fire count

    • waiver log

    Mini case study

    Block passed VIP compliance but chip failed: system test omitted cross-master ID reuse through a bridge. Scoreboard key did not include upstream port ID.

    Debug branches

    • If VIP pass but silicon fail, check integration assumptions.

    • If scoreboard noisy, fix key (ID+port+addr).

    • If coverage plateau, add compliance gap analysis not more repeats.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    PreviousNext: VIP & Agent Architecture: Mechanism

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    See also

    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan
    • Protocol Waveform Debug