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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
    • VIP & Agent Architecture
      • VIP & Agent Architecture: Mechanism
      • VIP & Agent Architecture: Inputs & Outputs
      • VIP & Agent Architecture: Reports & Metrics
      • VIP & Agent Architecture: Debug Playbook
      • VIP & Agent Architecture: Worked Example
      • VIP & Agent Architecture: Pitfalls & Red Flags
      • VIP & Agent Architecture: Interview Drills
      • VIP & Agent Architecture: Review Checklist
      • VIP & Agent Architecture: Theory Deep Dive
      • VIP & Agent Architecture: Design Space
      • VIP & Agent Architecture: Expanded Case Study
      • VIP & Agent Architecture: Step-by-Step Walkthrough
      • VIP & Agent Architecture: Comparison Matrix
      • VIP & Agent Architecture: Software / Programmer View
      • VIP & Agent Architecture: Silicon PPA Impact
    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan
    • Protocol Waveform Debug
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹VIP & Agent Architecture
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. VIP & Agent Architecture
  5. VIP & Agent Architecture: Review Checklist

Interface Protocols · All levels

VIP & Agent Architecture: Review Checklist

Review Checklist for VIP & Agent Architecture.

On this page

    Review checklist

    Review Checklist for VIP & Agent Architecture focuses on stimulus coverage, monitor mismatch rate, illegal sequence detection. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    • Spec revision and implemented feature subset are named.

    • Clock/reset and CDC assumptions are reviewed.

    • Traffic classes, IDs/tags, ordering, and outstanding limits are documented.

    • VIP/compliance coverage maps back to requirements.

    • Performance metric and debug artifact are stored with the signoff note.

    • Owners signed: verification lead, VIP owner, RTL owner.

    Sign-off ownership

    Diagram
    OWNERSHIP MAP — VIP & Agent Architecture
    
    evidence type        owner who reads it
    -----------------    ---------------------------
    waveform/RTL        verification lead
    spec/VIP            VIP owner
    firmware/system     RTL owner
    
    Rule: every metric must have a named owner before a review starts.

    Protocol deep dive

    Verification closes the gap between 'works in directed test' and 'legal under all stressed traffic'.

    Concept diagram

    Diagram
    VERIFICATION CLOSURE LOOP
    
    spec clause -> test -> assertion -> coverage -> waiver -> signoff
                      ^                           |
                      +--------- gap found --------+

    Metric graph

    Diagram
    COVERAGE vs ESCAPE RATE
    
    escapes
      |*
      | *
      |  *
      |   **  <- knee: more random helps
      |     ****
      +----------------> constrained-random depth

    Metrics and artifacts to collect

    • compliance pass rate

    • coverage closure

    • scoreboard mismatch rate

    • assertion fire count

    • waiver log

    Mini case study

    Block passed VIP compliance but chip failed: system test omitted cross-master ID reuse through a bridge. Scoreboard key did not include upstream port ID.

    Debug branches

    • If VIP pass but silicon fail, check integration assumptions.

    • If scoreboard noisy, fix key (ID+port+addr).

    • If coverage plateau, add compliance gap analysis not more repeats.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    Principal review addendum

    Re-read VIP & Agent Architecture against one concrete product workload, not a synthetic directed test.

    VIP separates driver, monitor, sequencer, checker, and coverage so protocol intent is observable and reusable.

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    See also

    • VIP & Agent Architecture: Mechanism
    • VIP & Agent Architecture: Inputs & Outputs
    • VIP & Agent Architecture: Reports & Metrics