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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC19
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
    • Stage 2: Clocks, Resets, Power
    • Stage 3: Interrupts and Boot
    • Stage 4: Verification and Signoff
    • Solutions
      • Root Causes, Fixes and Evidence
      • Stage 1 Worked Checks
      • Stage 2 Worked Checks
      • Stage 3 Worked Checks
      • Stage 4 Worked Checks
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←Capstone: Integrate NanoSoC
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC
  4. Solutions

Part 14 of 14Part 14 of 14/Capstone: Integrate NanoSoCAll levels

Solutions

The separated answer key: causes, fixes and evidence for the ten planted NanoSoC integration symptoms.

  • 5topics
  • 5lessons

Open this topic only after you have run the stage checks and written your own diagnoses. The brief intentionally gives symptoms only. This answer key maps each symptom to the NanoSoC fact, the corrective action and the evidence that should close the finding.

Lesson

After it you can...

Root Causes, Fixes and Evidence

Compare your diagnosis with the cause, fix and proof.

Stage 1 Worked Checks

Run the map, addressing and bandwidth examples after your investigation.

Stage 2 Worked Checks

Run the crossing, reset and isolation injections.

Stage 3 Worked Checks

Run the interrupt, driver and boot examples.

Stage 4 Worked Checks

Run the complete fault matrix and final manifest check.

A solution is not complete until the clean-data checker passes and the injected-bad case fails for the named reason.

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See also

  • Capstone Brief
  • Stage 1: Memory Map and Interconnect
  • Stage 2: Clocks, Resets, Power