One die stops being enough when the design outgrows its reticle, its yield curve or its process choice: logic wants the newest node, memory and analog do not. Splitting NanoSoC across two dies is deliberately oversized for a 0.585 mm2 chip — a teaching model, not a proposal — and that is its value: every budget in this section replayed across a die boundary, so the costs of the split are visible on numbers small enough to check. The first lesson shows that the cut a power engineer would draw first is the wrong one, the second prices the link the better cut creates, and the third re-anchors the test plan and every budget per die. This topic is the integrator's conceptual view of multi-die design.
Lesson | After it you can... |
|---|---|
Compare two candidate cuts by their crossing counts and say which one the data favours. | |
Price a die-to-die link in bandwidth, latency, power and bumps. | |
Explain known-good-die with equal-assumption yield numbers and re-anchor every budget per die. |
Suggested order: top to bottom. Choose the split, price the link it creates, then re-anchor the budgets and the test strategy. This is a conceptual view: interface standards for die-to-die links are covered at protocol level elsewhere, and this topic owns the integrator's question of what the split costs.
When yield, reticle size or process choice forces it: the saving on the split outweighs the link cost in power, latency, area and test. Never for convenience, and never at NanoSoC's size, where the numbers below show the link costs more than the split saves.