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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
    • Partitioning and Hierarchy
      • Flat Versus Hierarchical
      • Boundary Choices and Feedthroughs
      • NanoSoC Partition Rationale
    • Area Budgets
    • Timing Budgets Across Hierarchy
    • Power Budgets
    • Bandwidth Budgets
    • Budget Governance
    • Multi-Die and Chiplet View
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Architecture and Budgets
  1. Topics
  2. SoC Design
  3. Architecture and Budgets
  4. Partitioning and Hierarchy

Part 2 of 14Part 2 of 14/Architecture and BudgetsAll levels

Partitioning and Hierarchy

Flat versus hierarchical design, boundary choices, what crosses a boundary, feedthroughs, and why NanoSoC is split the way it is.

  • 3topics
  • 3lessons

A partition is a promise about what the tools and the team can handle as one piece: one synthesis run, one owner, one timing budget, one power intent. NanoSoC could be built flat — 16 blocks (15 modules plus the PLL macro) is small enough — but it is partitioned anyway, along its clock domains, its power domains and its protocol boundaries, because those are the seams where independent work actually pays. This topic teaches how to choose those seams, what is allowed to cross them, and why feedthroughs are a design smell worth counting.

Lesson

After it you can...

Flat Versus Hierarchical

Say when a design earns hierarchy and price its cost.

Boundary Choices and Feedthroughs

Decide what crosses a boundary and remove a feedthrough.

NanoSoC Partition Rationale

Defend every NanoSoC partition from clock, power and protocol reasons.

Suggested order: top to bottom. The first lesson decides whether hierarchy pays, the second polices the boundaries it creates, and the third applies both to NanoSoC. Where a boundary is also a clock domain boundary, the crossing rules come from CDC-Aware Partitioning. The physical side of the same decision lives in Partitioning a Block for Hierarchy; the RTL discipline in Top-down vs bottom-up integration.

Check yourself What does a partition boundary cost, in one sentence?

Every signal crossing it needs synchronising, budgeting, verifying and documenting, so a boundary must save more in parallel work and tool capacity than it spends in interface effort.

Expect to partition a small SoC on a whiteboard and justify each boundary three ways: clock, power and protocol.

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See also

  • Area Budgets
  • Timing Budgets Across Hierarchy
  • Power Budgets