Power is the budget that bites twice: once as energy the battery must supply, once as heat the package must remove. NanoSoC's numbers are fully worked — 82.74 mW in RUN, 16.89 mW in IDLE, 1.40 mW in SLEEP, with the CPU core alone nearly half the RUN total — and this topic teaches how to roll them up per domain and state, how to prove the package can carry the heat (against an illustrative thermal limit, since the NanoSoC specification defines none), and how to compare the budget against silicon without fooling yourself. For the physics behind switching and leakage power see Power and Energy.
Lesson | After it you can... |
|---|---|
Roll the block table to per-domain and per-state totals that add up. | |
Prove the chip fits its thermal envelope or say what throttles first. | |
Compare budget against silicon and explain the gap honestly. |
Suggested order: top to bottom. Add the power up first, then check the heat it makes, then learn how measurement revises the budget. The deeper power-architecture treatment of thermal control lives in the power-architecture section; this topic teaches the full envelope check the integrator must run regardless.
Because RUN and SLEEP differ by about 59x on NanoSoC (82.74 versus 1.40 mW). One number either oversizes the supply or melts the package; the state table sizes each correctly.