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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
    • Partitioning and Hierarchy
    • Area Budgets
    • Timing Budgets Across Hierarchy
    • Power Budgets
      • Dynamic and Leakage Roll-Up
      • Thermal and Power Envelope
      • Budget Versus Measured
    • Bandwidth Budgets
    • Budget Governance
    • Multi-Die and Chiplet View
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Architecture and Budgets
  1. Topics
  2. SoC Design
  3. Architecture and Budgets
  4. Power Budgets

Part 2 of 14Part 2 of 14/Architecture and BudgetsAll levels

Power Budgets

Dynamic and leakage roll-up per domain and state, the thermal and power envelope, and budget versus measured.

  • 3topics
  • 3lessons

Power is the budget that bites twice: once as energy the battery must supply, once as heat the package must remove. NanoSoC's numbers are fully worked — 82.74 mW in RUN, 16.89 mW in IDLE, 1.40 mW in SLEEP, with the CPU core alone nearly half the RUN total — and this topic teaches how to roll them up per domain and state, how to prove the package can carry the heat (against an illustrative thermal limit, since the NanoSoC specification defines none), and how to compare the budget against silicon without fooling yourself. For the physics behind switching and leakage power see Power and Energy.

Lesson

After it you can...

Dynamic and Leakage Roll-Up

Roll the block table to per-domain and per-state totals that add up.

Thermal and Power Envelope

Prove the chip fits its thermal envelope or say what throttles first.

Budget Versus Measured

Compare budget against silicon and explain the gap honestly.

Suggested order: top to bottom. Add the power up first, then check the heat it makes, then learn how measurement revises the budget. The deeper power-architecture treatment of thermal control lives in the power-architecture section; this topic teaches the full envelope check the integrator must run regardless.

Check yourself Why does power need a per-state table rather than one number?

Because RUN and SLEEP differ by about 59x on NanoSoC (82.74 versus 1.40 mW). One number either oversizes the supply or melts the package; the state table sizes each correctly.

Expect to name the largest power item and the largest state-to-state change. On NanoSoC: the CPU core in RUN, and the roughly 59x drop from RUN to SLEEP.

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See also

  • Partitioning and Hierarchy
  • Area Budgets
  • Timing Budgets Across Hierarchy