A path that crosses three blocks has one clock period and three owners, and each owner spends part of it. NanoSoC's slowest fabric paths are fully priced — a CPU fetch costs 18 cpu clocks totalling 93.75 ns, a peripheral read costs 281.25 ns across three domains — and this topic teaches how to split such latencies into per-block cycle budgets (what software waits for), how a path inside one clock period is budgeted differently (setup time between blocks), how to budget the chip's I/O timing against the board, and how to hold margin so one block's miss does not become a chip miss. For the analysis mechanics behind these numbers see the STA course; here the integrator decides the allowances.

Suggested order: top to bottom. Price the internal paths first, then the pins, then the margin that protects both. For boundary timing from the layout side see I/O Timing and Block Boundaries; for interface budgets in constraint form see Interface Budgets.