Late in a project someone asks whether two core supply pads can be dropped to save package cost, and without a budget the answer is an opinion. With one, the answer is arithmetic: the RUN current divided by the per-pad limit, rounded up, at the average and at the peak, and dropping a pad visibly breaks the inequality. The same budget answers a second question, whether the die size follows the core or the pads. This lesson builds both for NanoSoC from numbers the NanoSoC power and area tables actually give.
The pad total has two parts: signal pads from the pin list (19 on NanoSoC, of which two are the analog crystal pads), and supply pads computed from current and placement. The RUN total on NanoSoC is 82.74 mW on a 0.9 V rail, so the core current is 82.74 divided by 0.9, 91.93 mA. Each supply pad is allowed an illustrative 50 mA, a package-specific limit used here as the calculator input. At the average, ceil(91.93 / 50) = 2 pads would do. But the rail sees short peaks above the average, and the pad limit has to hold there too: with an illustrative peak-to-average factor of 2.0 the peak is 183.87 mA and ceil(183.87 / 50) = 4. NanoSoC therefore has four core supply pads, 46 mA each at the peak, each with its own ground return, which makes 8 pads. The two I/O supply pairs are not sized by current but by switching noise, which is the next lesson: 2 x 2 = 4 more pads, 12 supply pads in all.
The second question is whether the perimeter holds the pads. The die budget in the NanoSoC area table is 0.940 mm², which treated as a square is 0.9695 mm on a side, so a perimeter of 3.878 mm. After a corner keep-out of 60 µm at each end, one side has 849.5 µm of usable length, which at an illustrative 80 µm pad pitch is 10 pad slots, 40 in all. Thirty-one pads need 31 x 0.080 = 2.480 mm, which is 63.9% of the perimeter and 73.0% of the usable length, leaving 9 spare slots. NanoSoC is core-limited, not pad-limited: the logic fixes the die size, and removing a pin would not shrink the die. It would become pad-limited only above 40 pads at this pitch, or if the pitch grew above 109.6 µm. The smallest square that holds 31 pads is 760 µm a side, 0.578 mm², well below the 0.940 mm² the core needs. (The 0.655 mm² of cell area in the area table is before the utilisation overhead; the die budget is the right comparison.)
This perimeter test treats the pads as a ring around the core, as a wire-bonded die has. It is the conservative case for a package that is not area-array on the die: with flip-chip bumps spread over the die face the die size would be set by the core alone, and the answer would only get better for NanoSoC.
The script below computes the core supply pads at the average and at the peak, rebuilds the 12 supply pads and the 31 total, and runs the perimeter test with the numbers above. It also runs the same functions on cases that must fail: two core supply pads (enough for the average, not for the peak), a 120 µm pitch, and a 41-pad design.
import math
RUN_MW, VDD = 82.74, 0.9
I_AVG = RUN_MW / VDD # 91.93 mA
PEAK_FACTOR, PER_PAD_MA = 2.0, 50.0 # illustrative teaching inputs
I_PEAK = I_AVG * PEAK_FACTOR # 183.87 mA
SIGNAL = 16 + 1 + 2
IO_PAIRS = 2
DIE_MM2, KEEPOUT_UM = 0.940, 60.0
def core_pads_ok(n):
return n * PER_PAD_MA >= I_AVG and n * PER_PAD_MA >= I_PEAK
def core_limited(pads, pitch_um):
side_um = math.sqrt(DIE_MM2) * 1000
slots = 4 * math.floor((side_um - 2 * KEEPOUT_UM) / pitch_um)
return pads * pitch_um / 1000 <= 4 * side_um / 1000 and pads <= slots
need_avg = math.ceil(I_AVG / PER_PAD_MA)
need_peak = math.ceil(I_PEAK / PER_PAD_MA)
assert (need_avg, need_peak) == (2, 4), (need_avg, need_peak)
assert round(I_AVG, 2) == 91.93 and round(I_PEAK, 2) == 183.87
assert core_pads_ok(4) and not core_pads_ok(2) and not core_pads_ok(3)
supply = 2 * need_peak + 2 * IO_PAIRS
assert supply == 12 and SIGNAL + supply == 31, (SIGNAL, supply)
assert round(math.sqrt(DIE_MM2), 4) == 0.9695
assert core_limited(31, 80)
assert 4 * math.floor((math.sqrt(DIE_MM2) * 1000 - 2 * KEEPOUT_UM) / 80) - 31 == 9 # spare slots
assert round(31 * 0.080, 3) == 2.480 and 63.9 <= 100 * 2.480 / 3.878 < 64.0
assert not core_limited(31, 120) # pitch above 109.6 um would make it pad-limited
assert not core_limited(41, 80) # more than 40 slots
print("PASS: 4 core supply pads (2 would pass the average, fail the peak); 31 pads; core-limited, 9 spare slots")The current quoted from the NanoSoC power table with the division shown, not a current invented for the lesson.
Every supply pad justified: average current, peak current, and which sizing rule (current or switching noise) set it.
The pad-limited verdict stated against the die budget, with the spare slots counted, so a later pin addition can be priced.
Recompute the current twice: once from the RUN row, once as the sum of the per-block powers; both must give the same total before the budget means anything. If a re-spin raises RUN power, the budget is re-run, not re-argued: the script takes the new total and either still passes or names the extra pad. Re-run the perimeter test whenever the die budget or the pad pitch changes.
Because the limit has to hold at the peak: 183.87 mA over two pads is 92 mA each, above the 50 mA limit, and three pads (61 mA) still fail. Four give 46 mA each, and also one feed on each of the four quadrants of the die.