STA Mastery · All levels
Constraints & SDC Fundamentals: Tricky Q&A
Senior interview and review questions for Constraints & SDC Fundamentals.
Section Q&A bank
Use these drills after completing all topics in Constraints & SDC Fundamentals. Answer with corner/mode/view, path group, metric, artifact, ECO, and regression.
What is setup slack?
diagram
[INT][STA][CONSTRAINTS-FUNDAMENTALS]
Q: What is setup slack?
A:
Required time minus arrival time on the max-delay (setup) path; negative means failing setup.
FOLLOW-UP TRAP: Confusing setup with hold.Why is clock uncertainty used?
diagram
[INT][STA][CONSTRAINTS-FUNDAMENTALS]
Q: Why is clock uncertainty used?
A:
To model jitter, skew, and margin not captured elsewhere before evaluating path delay.
FOLLOW-UP TRAP: Setting uncertainty to zero for optimism.When is a false_path justified?
diagram
[INT][STA][CONSTRAINTS-FUNDAMENTALS]
Q: When is a false_path justified?
A:
When the path is physically impossible or logically irrelevant to functional modes — must be documented.
FOLLOW-UP TRAP: Using false_path to hide real paths.What does set_input_delay model?
diagram
[INT][STA][CONSTRAINTS-FUNDAMENTALS]
Q: What does set_input_delay model?
A:
External delay from board/pad to the chip input flop — part of the IO timing contract.
FOLLOW-UP TRAP: Forgetting output delays on outputs.Q&A drill guide
diagram
CONSTRAINT -> VIEW -> PATH -> METRIC -> ECO -> REGRESSIONSketch while answering
diagram
SDC FLOW
RTL clocks -> create_clock / generated_clock
board -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis -> report_timingKey takeaways
State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.
Common pitfalls
Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.