I/O Timing & Boundary Contracts: Expanded Case Study

Extended case study

Signoff review: interface setup/hold WNS, input/output delay coverage, port slack fails after an apparently minor change affecting I/O Timing & Boundary Contracts.

Background

Team had closure last week on full MMMC matrix. New run shows regression clustered in one path group.

Symptoms observed

• interface setup/hold WNS, input/output delay coverage, port slack regression

• Disagreement between synth and STA WNS

• Hold violations after setup ECO

Investigation timeline

1. Hour 0: freeze netlist, SDC, SPEF, lib tags

2. Hour 1: diff constraints and run manifest

3. Hour 2: isolate corner/mode that fails

4. Hour 3: read worst path — cell vs net, clocks

5. Hour 4: classify root cause

6. Hour 5: minimal ECO or SDC fix

7. Hour 6: full regression + signoff memo

Root cause

Root cause tied to I/O Timing & Boundary Contracts: set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing.

Fix and validation

• Bounded ECO or audited SDC change

• Re-run boundary SDC, board delay spreadsheet, report_timing on IO paths

• Full MMMC + SI regression

Lessons learned

• Tag every run

• Diff constraints before blaming PD

• Setup and hold together

CASE STUDY — I/O Timing & Boundary Contracts
baseline WNS / regressed WNS / post-fix WNS

Sequence under stress

TIMING PATH — I/O Timing & Boundary Contracts

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: interface setup/hold WNS, input/output delay coverage, port slack

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing.

Metric: interface setup/hold WNS, input/output delay coverage, port slack