STA Mastery · All levels
I/O Timing & Boundary Contracts: Review Checklist
Review Checklist for I/O Timing & Boundary Contracts.
Review checklist
Review Checklist for I/O Timing & Boundary Contracts focuses on interface setup/hold WNS, input/output delay coverage, port slack. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.
SDC revision and implemented clock/exception policy are named.
Clock/reset and CDC assumptions are reviewed.
Path groups, IO delays, and exception rationale are documented.
MMMC scenario list maps back to signoff requirements.
WNS/TNS artifact stored with corner/mode/view tags.
Owners signed: STA owner, package owner, system integration owner.
Sign-off ownership
OWNERSHIP MAP — I/O Timing & Boundary Contracts
artifact owner
---------------- -----------------
timing report STA owner
SDC/constraint package owner
implementation system integration owner
Every WNS cluster needs a named owner before ECO.STA deep dive
SDC quality determines whether STA measures reality or fiction.
Concept diagram
SDC FLOW
RTL clocks -> create_clock / generated_clock
board -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis -> report_timingMetric graph
CONSTRAINT QUALITY
audited exceptions ████████████████ good
stale IO delays ██████ risk
missing gen clock ████ high escapeReports and artifacts
clock report
uncertainty budget
IO delay coverage
exception audit log
Mini case study
1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.
Debug branches
Diff SDC before ECO
Validate clocks on failing path
Audit false paths quarterly
Senior review question
Ask: what corner/mode/view proves this topic is closed or failing?
Key takeaways
State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.
Common pitfalls
Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.
Principal STA review addendum
set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing.
Metric: interface setup/hold WNS, input/output delay coverage, port slack