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I/O Timing & Boundary Contracts: Comparison Matrix

Comparison Matrix for I/O Timing & Boundary Contracts.

Comparison matrix

Constraint choices trade pessimism, coverage, and debug complexity.

diagram

+------------------+----------------+----------------+----------------+
| Approach         | Strength       | Weakness       | Best when      |
+------------------+----------------+----------------+----------------+
| Conservative     | safe           | slow closure   | risk-averse    |
| Balanced         | practical      | needs discipline | production     |
| Aggressive       | fast           | regression risk | tapeout crunch |
| RTL change       | structural     | long loop      | architectural  |
+------------------+----------------+----------------+----------------+

When to choose each approach

Match approach to schedule and silicon risk

Interview traps

One-size ECO playbook
Ignoring hold

Evidence comparison

diagram

STA EVIDENCE MATRIX — I/O Timing & Boundary Contracts

+-------------------+------------------------+--------------------------+-------------------------+
| Evidence           | Tells you              | Does not prove           | Next action             |
+-------------------+------------------------+--------------------------+-------------------------+
| report_timing      | critical path slack    | root cause class         | cell vs net split       |
| clock report       | clock reachability     | path delay               | fix generated_clock     |
| SDC diff           | constraint change      | physical delay           | re-run all scenarios    |
| SPEF tag compare   | parasitic view         | constraint quality       | isolate view mismatch   |
| MMMC dashboard     | worst scenario         | single-path fix          | assign path group owner |
+-------------------+------------------------+--------------------------+-------------------------+

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

diagram

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

clock report
uncertainty budget
IO delay coverage
exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

Diff SDC before ECO
Validate clocks on failing path
Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.

Principal STA review addendum

set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing.

Metric: interface setup/hold WNS, input/output delay coverage, port slack

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