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I/O Timing & Boundary Contracts: Interview Drills

Interview Drills for I/O Timing & Boundary Contracts.

Interview drills

Interview Drills for I/O Timing & Boundary Contracts focuses on interface setup/hold WNS, input/output delay coverage, port slack. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

diagram

PROMPT
You see interface setup/hold WNS, input/output delay coverage, port slack on I/O Timing & Boundary Contracts. Walk through root cause and fix.

STRONG ANSWER
1. Names corner/mode/view and path group.
2. Explains set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing.
3. Requests boundary SDC, board delay spreadsheet, report_timing on IO paths.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to upsizing cells, widening routes, or blaming tools without reading constraints and path delay.

Diagram to draw on the whiteboard

Input / output delay model

diagram

BOARD                    CHIP BOUNDARY              INTERNAL
  |                            |                          |
pad delay -- set_input_delay -> FF capture path analyzed by STA
internal launch -- set_output_delay -> pad delay -> board

IO constraints are the contract between system and block STA.

Root-cause tree to narrate

diagram

ROOT-CAUSE TREE — I/O Timing & Boundary Contracts

interface setup/hold WNS, input/output delay coverage, port slack looks wrong
        |
   same netlist tag?
     /        \
   no          yes
   |            |
 view/SDC     real path or
 mismatch     constraint bug
 /    \           |
lib   SPEF    delay breakdown
diff  diff    cell vs net

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

diagram

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

clock report
uncertainty budget
IO delay coverage
exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

Diff SDC before ECO
Validate clocks on failing path
Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.

Principal STA review addendum

set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing.

Metric: interface setup/hold WNS, input/output delay coverage, port slack

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