I/O Timing & Boundary Contracts: Mechanism

Mechanism to understand

Mechanism for I/O Timing & Boundary Contracts focuses on interface setup/hold WNS, input/output delay coverage, port slack. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing. Think of STA as a signed contract between constraints, parasitics, and implementation — slack is the measurable outcome.

• Identify launch and capture clocks on the failing path.

• Identify path group: reg2reg, in2reg, reg2out, or async.

• Identify whether setup, hold, or both fail in the scenario.

Layered view

STA CLOSURE FLOW — I/O Timing & Boundary Contracts

constraints (SDC)
        |
        v
timing graph (cell + net delays)
        |
        v
MMMC scenarios (corner x mode x view)
        |
        v
variation + SI adjustments
        |
        v
slack (WNS/TNS) -> ECO -> regression

Debug rule: always state corner, mode, view, and database tag with slack.

Input / output delay model

BOARD                    CHIP BOUNDARY              INTERNAL
  |                            |                          |
pad delay -- set_input_delay -> FF capture path analyzed by STA
internal launch -- set_output_delay -> pad delay -> board

IO constraints are the contract between system and block STA.

Layer responsibilities

STA OWNERSHIP LAYERS — I/O Timing & Boundary Contracts

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Mechanism deep dive

set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing.