I/O Timing & Boundary Contracts: Theory Deep Dive

Foundational theory

I/O Timing & Boundary Contracts is central to Constraints & SDC Fundamentals. set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing. Senior STA engineers always tie slack movement to corner, mode, constraint set, and parasitic view — not just a single report line.

Core concepts explained

• set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing.

• Primary metric: interface setup/hold WNS, input/output delay coverage, port slack

• Primary artifact: boundary SDC, board delay spreadsheet, report_timing on IO paths

• Owners: STA owner, package owner, system integration owner

• Setup: max delay path; Hold: min delay path

• WNS/TNS summarize tail risk across endpoints

Why this matters at signoff

At signoff, I/O Timing & Boundary Contracts failures block tapeout or force risky ECO. SDC is the contract between RTL intent, synthesis, and signoff STA. Wrong analysis setup wastes weeks of PD effort.

Mental model

BOARD                    CHIP BOUNDARY              INTERNAL
  |                            |                          |
pad delay -- set_input_delay -> FF capture path analyzed by STA
internal launch -- set_output_delay -> pad delay -> board

IO constraints are the contract between system and block STA.

Worked intuition

1. Name corner, mode, and view for the failing run.

2. Open interface setup/hold WNS, input/output delay coverage, port slack and identify worst path group.

3. Read critical path: cell vs net, launch/capture clocks.

4. Check constraints on that path (exceptions, generated clocks).

5. Collect boundary SDC, board delay spreadsheet, report_timing on IO paths and tag database versions.

6. Classify: constraint bug, view mismatch, or real path.

7. Propose minimal ECO and list MMMC+SI regression.

Common misconceptions

• One typical corner is enough for signoff.

• False paths can be applied broadly to green-wash violations.

• Implementation WNS equals signoff WNS without view mapping.

• Setup fix automatically preserves hold.

Visual reinforcement

Input / output delay model

BOARD                    CHIP BOUNDARY              INTERNAL
  |                            |                          |
pad delay -- set_input_delay -> FF capture path analyzed by STA
internal launch -- set_output_delay -> pad delay -> board

IO constraints are the contract between system and block STA.

Layer responsibilities

STA OWNERSHIP LAYERS — I/O Timing & Boundary Contracts

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Theory reinforcement

SDC is the contract between RTL intent, synthesis, and signoff STA.