I/O Timing & Boundary Contracts: Worked Example

Worked example

Worked Example for I/O Timing & Boundary Contracts focuses on interface setup/hold WNS, input/output delay coverage, port slack. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

A signoff run shows interface setup/hold WNS, input/output delay coverage, port slack. The first review mistake is to blame implementation without checking constraints. A better review starts by pinning one critical path, proving where slack was lost, and checking whether the SDC rule is correct for I/O Timing & Boundary Contracts.

Sequence under inspection

TIMING PATH — I/O Timing & Boundary Contracts

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: interface setup/hold WNS, input/output delay coverage, port slack

Input / output delay model

BOARD                    CHIP BOUNDARY              INTERNAL
  |                            |                          |
pad delay -- set_input_delay -> FF capture path analyzed by STA
internal launch -- set_output_delay -> pad delay -> board

IO constraints are the contract between system and block STA.

1. Capture report_timing and the relevant SDC excerpt.

2. Tag corner, mode, view, and path group.

3. Find the first cell or net that dominates critical delay.

4. Compare against boundary SDC, board delay spreadsheet, report_timing on IO paths.

5. Choose one reversible ECO and write the regression matrix before editing netlist or constraints.

Did the fix work?

BEFORE / AFTER ECO — I/O Timing & Boundary Contracts

WNS (ps)
  0 |                    --- target
-50 |    ● regressed
-80 |         ● before ECO
-20 |              ● after ECO
    +-------------------------------> ECO iteration
Prove setup AND hold moved safely.

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

set_input_delay and set_output_delay translate board and pad timing into the block boundary so internal STA matches system timing.

Metric: interface setup/hold WNS, input/output delay coverage, port slack