STA Mastery · All levels

Cell vs Net Delay Budgets: Review Checklist

Review Checklist for Cell vs Net Delay Budgets.

Review checklist

Review Checklist for Cell vs Net Delay Budgets focuses on cell delay %, net delay %, high fanout net count, transition violations. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

SDC revision and implemented clock/exception policy are named.
Clock/reset and CDC assumptions are reviewed.
Path groups, IO delays, and exception rationale are documented.
MMMC scenario list maps back to signoff requirements.
WNS/TNS artifact stored with corner/mode/view tags.
Owners signed: PD owner, STA owner, extraction owner.

Sign-off ownership

diagram

OWNERSHIP MAP — Cell vs Net Delay Budgets

artifact              owner
----------------      -----------------
timing report       PD owner
SDC/constraint      STA owner
implementation      extraction owner

Every WNS cluster needs a named owner before ECO.

STA deep dive

Slack is a path story — read the graph, not just the number.

Concept diagram

diagram

TIMING GRAPH

FF --cell-- logic --net-- logic --cell-- FF
launch                              capture

Metric graph

diagram

SLACK TAIL

paths |    ***
      |  *******
      |*********  <- fix WNS first

Reports and artifacts

WNS/TNS
path slack histogram
cell vs net %
path group summary

Mini case study

WNS -90ps but 80% net delay on one congested route — PD route fix beat upsizing three cells.

Debug branches

Cell-heavy -> sizing/VT
Net-heavy -> route/layer
Check launch/capture clocks

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.

Principal STA review addendum

Path delay splits between library cell arcs and interconnect parasitics; implementation fixes target the dominant contributor.

Metric: cell delay %, net delay %, high fanout net count, transition violations

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