STA Mastery · All levels

Cell vs Net Delay Budgets: Design Space

Design Space for Cell vs Net Delay Budgets.

Design space exploration

For Cell vs Net Delay Budgets, closure options trade margin, schedule, and regression risk.

Option A — conservative

Conservative margin: helps safe signoff
Risk: over-pessimism, area/power
Validate with: first silicon

Option B — balanced

Balanced derate: helps reasonable margin
Risk: needs approval
Validate with: mature node

Option C — aggressive ECO

Aggressive ECO: helps fast WNS gain
Risk: hold/SI regressions
Validate with: late schedule

Option D — RTL restructure

RTL restructure: helps structural fix
Risk: schedule hit
Validate with: chronic paths

diagram

DESIGN SPACE — Cell vs Net Delay Budgets
margin <-> performance <-> schedule
pick based on cell delay %, net delay %, high fanout net count, transition violations on product scenarios

Design pitfalls

ECO without regression matrix
Constraint change without audit

Tradeoff curve

diagram

BEFORE / AFTER ECO — Cell vs Net Delay Budgets

WNS (ps)
  0 |                    --- target
-50 |    ● regressed
-80 |         ● before ECO
-20 |              ● after ECO
    +-------------------------------> ECO iteration
Prove setup AND hold moved safely.

STA deep dive

Slack is a path story — read the graph, not just the number.

Concept diagram

diagram

TIMING GRAPH

FF --cell-- logic --net-- logic --cell-- FF
launch                              capture

Metric graph

diagram

SLACK TAIL

paths |    ***
      |  *******
      |*********  <- fix WNS first

Reports and artifacts

WNS/TNS
path slack histogram
cell vs net %
path group summary

Mini case study

WNS -90ps but 80% net delay on one congested route — PD route fix beat upsizing three cells.

Debug branches

Cell-heavy -> sizing/VT
Net-heavy -> route/layer
Check launch/capture clocks

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.

Principal STA review addendum

Path delay splits between library cell arcs and interconnect parasitics; implementation fixes target the dominant contributor.

Metric: cell delay %, net delay %, high fanout net count, transition violations

Practice this lesson