STA Mastery · All levels
Cell vs Net Delay Budgets: Pitfalls & Red Flags
Pitfalls & Red Flags for Cell vs Net Delay Budgets.
Pitfalls and red flags
Pitfalls & Red Flags for Cell vs Net Delay Budgets focuses on cell delay %, net delay %, high fanout net count, transition violations. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.
A path looks clean in one view but fails in signoff SPEF.
The SDC allows behavior that the implementation team assumed was illegal.
A generated_clock definition shifts capture edge silently.
Hold fails on short paths after setup-focused ECO.
The fix improves one corner but regresses another MMMC scenario.
Layer responsibility check
STA OWNERSHIP LAYERS — Cell vs Net Delay Budgets
layer owns failure mode
---------------- -------------------------- ---------------------
constraints clocks, IO, exceptions false violations
implementation cells, nets, placement real path delay
extraction SPEF/RC corners view mismatch
signoff policy derate, MMMC matrix margin disputes
closure ECO order, regression fix breaks other cornerSTA deep dive
Slack is a path story — read the graph, not just the number.
Concept diagram
TIMING GRAPH
FF --cell-- logic --net-- logic --cell-- FF
launch captureMetric graph
SLACK TAIL
paths | ***
| *******
|********* <- fix WNS firstReports and artifacts
WNS/TNS
path slack histogram
cell vs net %
path group summary
Mini case study
WNS -90ps but 80% net delay on one congested route — PD route fix beat upsizing three cells.
Debug branches
Cell-heavy -> sizing/VT
Net-heavy -> route/layer
Check launch/capture clocks
Senior review question
Ask: what corner/mode/view proves this topic is closed or failing?
Key takeaways
State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.
Common pitfalls
Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.
Principal STA review addendum
Path delay splits between library cell arcs and interconnect parasitics; implementation fixes target the dominant contributor.
Metric: cell delay %, net delay %, high fanout net count, transition violations