STA Mastery · All levels
Cell vs Net Delay Budgets: Step-by-Step Walkthrough
Step-by-Step Walkthrough for Cell vs Net Delay Budgets.
Step-by-step analysis walkthrough
Use when you own Cell vs Net Delay Budgets in a timing war room.
Open signoff scenario list — note worst WNS corner.
report_timing -max/-min on failing group.
Trace launch and capture clocks on critical path.
Check exceptions and generated clocks on path.
Break down cell vs net delay.
Compare implementation vs signoff view if delta suspicious.
Assign owner: RTL, synth, PD, CTS, SI.
Propose ECO with hold/SI check plan.
Run regression matrix.
Update closure dashboard and memo.
Artifacts to collect
report_timing -cap -tran -nets, delay breakdown report, RC extraction log
SDC file
SPEF tag
MMMC scenario list
ECO ticket
Decision memo template
STA DECISION MEMO — Cell vs Net Delay Budgets
corner/mode:
WNS/TNS:
hypothesis:
ECO:
regression:
owners: PD owner, STA owner, extraction ownerReference visuals
Delay breakdown bar
PATH DELAY BREAKDOWN
cell delay ████████████████ 62%
net delay ██████████ 38%
If net-heavy -> routing/RC fix.
If cell-heavy -> sizing/VT/upsize.STA deep dive
Slack is a path story — read the graph, not just the number.
Concept diagram
TIMING GRAPH
FF --cell-- logic --net-- logic --cell-- FF
launch captureMetric graph
SLACK TAIL
paths | ***
| *******
|********* <- fix WNS firstReports and artifacts
WNS/TNS
path slack histogram
cell vs net %
path group summary
Mini case study
WNS -90ps but 80% net delay on one congested route — PD route fix beat upsizing three cells.
Debug branches
Cell-heavy -> sizing/VT
Net-heavy -> route/layer
Check launch/capture clocks
Senior review question
Ask: what corner/mode/view proves this topic is closed or failing?
Key takeaways
State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.
Common pitfalls
Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.
Principal STA review addendum
Path delay splits between library cell arcs and interconnect parasitics; implementation fixes target the dominant contributor.
Metric: cell delay %, net delay %, high fanout net count, transition violations